Patent
1995-11-08
1998-11-03
Harvey, Jack B.
39580034, 395562, 395306, G06F 1200
Patent
active
058322485
ABSTRACT:
A logic LSI chip includes a CPU, a bus, a memory, and a multiplier. In addition, the logic LSI chip includes a command signal line for transferring, from the CPU to the multiplier, a command regarding a multiplication instruction relating to data read out, while the data is being read out from the memory, so that the multiplier can fetch the data directly from the bus. While the CPU is reading data from the memory, therefore, a command of a multiplication instruction relating to data read out is transferred from the CPU to the multiplier. A bus cycle control circuit receives a state signal from the multiplier when the multiplier is executing a repetitional operation and the bus cycle control circuit responds to the state signal by signalling the CPU to delay issuance of a succeeding command to the multiplier.
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Akao Yasushi
Kawasaki Shumpei
Kishi Kazumasa
Masumura Shigeki
Nakamura Hideo
Harvey Jack B.
Hitachi , Ltd.
Hitachi ULSI Engineering Co., Ltd.
Seto Jeffrey K.
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