Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2005-03-01
2005-03-01
Mai, Son (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S145000, C365S149000, C365S065000, C365S069000
Reexamination Certificate
active
06862204
ABSTRACT:
A plurality of memory cell arrays includes bit lines and memory cells each constituted by a variable capacitor, and operates at mutually different timings. The bit lines of each memory cell array are connected to bit lines of the other memory cell arrays via connecting wires. Accordingly, the actual capacitances of the bit lines are the capacitances of bit lines of that memory cell array itself plus that of the other memory cell arrays plus the capacitances of the connecting wires. Therefore, when data is read from the memory cells, the variations in voltage of the bit lines caused by the capacitive division can be enlarged. Consequently, the read margin can be prevented from being degraded, and the manufacturing yield of semiconductor memories can be prevented from being degraded. Additionally, since the variations in voltage of the bit lines are enlarged, the data reading time can be shortened.
REFERENCES:
patent: 5870343 (1999-02-01), Chi et al.
patent: 6201272 (2001-03-01), Kotecki et al.
patent: 6600674 (2003-07-01), Kasai
European Search Report dated Mar. 23, 2004.
Arent & Fox PLLC
Mai Son
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