Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-11-30
2002-07-23
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S189050
Reexamination Certificate
active
06424592
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuits and particularly to a semiconductor integrated circuit having a circuit for correcting data output timing.
2. Description of the Background Art
Dynamic random access memory DRAM has been known as the one achieving a high-speed operation. Such a DRAM (hereinafter referred to as semiconductor integrated circuit) is structured to include a DLL (delayed locked loop) circuit for outputting a multiple number of data at the same timing based on an internal clock signal supplied from the DLL circuit.
One example of such a conventional semiconductor integrated circuit is described in conjunction with FIG.
28
. The conventional semiconductor integrated circuit
5000
includes a DLL circuit
501
generating internal clock signal DLLCLK for determining the timing of an internal operation, clock generators PX
0
-PX
7
, and output buffers
502
#
0
-
502
#
7
.
Output buffer
502
#i receives read data RDi and ZRDi from a data input/output line L to output corresponding data to a data input/output pin DQ (i) (i=0-7). In
FIG. 28
, RD (0:7) represents RD
0
, . . . , RD
7
and ZRD (0:7) represents ZRD
0
, . . . , ZRD
7
.
Clock generators PX
0
-PX
7
have the same structures respectively. The clock generators respectively generate output clock signals CLKQ (
0
)-CLKQ (
7
) based on internal clock signal DLLCLK received via a line
101
. Output clock signals CLKQ (
0
)-CLKQ (
7
) determine timing of outputting data from respective output buffers
502
#-
502
#
7
.
This structure allows 8-bit output data DQ (
0
)-DQ (
7
) to be supplied to any external unit at a time.
In such a semiconductor integrated circuit, any load of line
101
causes difference in arrival time of internal clock signal DLLCLK at respective clock generators PX
0
-PX
7
.
Specifically, clock generator PX
3
located closest to DLL circuit
501
and clock generator PX
0
remotest from DLL circuit
501
are different in the length of line for receiving internal dock signal DLLCLK. Therefore, clock generators PX
3
and PX
0
receive internal clock signal DLLCLK at different times respectively and consequently there is generated a certain difference between respective output clock signals. As a result, data are output from respective data input/output pins DQ (
0
) and DQ (
3
) at different times.
For the DRAM operating at high speed, data output timing (time tAC) is severely defined. Therefore, for the structure of the conventional semiconductor integrated circuit, a skew between DQs is likely to be out of the range of specification.
Since this skew depends on noise and process of peripheral circuitry, the output timing has been adjusted by revise of a mask and the like. Nevertheless, this measure cannot overcome the skew occurring in the actual environment.
SUMMARY OF THE INVENTION
The present invention accordingly provides a semiconductor integrated circuit having a function of correcting data output timing.
According to one aspect of the invention, a semiconductor integrated circuit includes a memory cell array having a plurality of memory cells, a plurality of data output pins, a plurality of output buffers provided correspondingly to respective data output pins to output data read from the memory cell array to corresponding data output pins respectively, an internal clock generator generating an internal clock signal, a plurality of clock generators provided correspondingly to respective output buffers to generate an output clock signal determining output timing of a corresponding output buffer based on the internal clock signal, and a correction circuit correcting a skew in data output timing between the data output pins.
Preferably, the correction circuit includes a detection circuit detecting the skew in data output timing between the data output pins and the clock generators include a variable clock generator generating the output clock signal having its phase varied according to an output of the detection circuit.
In particular, the detection circuit detects difference in phase between an output dock signal supplied from a clock generator where the internal clock signal arrives latest and an output clock signal supplied from a clock generator where the internal clock signal arrives earliest.
In particular, the variable clock generator includes a plurality of generators generating based on the internal dock signal respective output dock signals having respective phases different from each other, and one of the generators is selectively operated according to the output of the detection circuit.
Preferably, the clock generators include a variable clock generator having a plurality of generators generating based on the internal clock signal respective output clock signals with respective phases different from each other, and the correction circuit selectively operates one of the generators to allow output timing of the clock generators to conform to output timing of a clock generator where the internal clock signal arrives latest.
Preferably, the clock generators include a variable clock generator having a plurality of generators generating based on the internal clock signal respective output clock signals with respective phases different from each other, and the correction circuit selectively operates one of the generators to allow output timing of the clock generators to conform to output timing of a clock generator where the internal clock signal arrives earliest.
In particular, the clock generators include a clock generator where the internal clock signal arrives latest and a variable clock generator having a plurality of generators generating based on the internal clock signal respective output clock signals with respective phases different from each other. The detection circuit includes a first circuit imitating an output of the clock generator where the internal clock signal arrives latest, a second circuit imitating respective outputs of the generators, a phase comparator comparing phase of an output of the first circuit with phase of an output of the second circuit, and a circuit for selecting any of respective outputs of the generators that is closest to the output of the clock generator where the internal clock signal arrives latest according to result of the phase comparison. Alternatively, the clock generators include a clock generator where the internal clock signal arrives earliest and a variable clock generator having a plurality of generators generating based on the internal clock signal respective output clock signals with respective phases different from each other. The detection circuit includes a first circuit imitating an output of the clock generator where the internal clock signal arrives earliest, a second circuit imitating respective outputs of the generators, a phase comparator comparing phase of an output of the first circuit with phase of an output of the second circuit, and a circuit for selecting any of respective outputs of the generators that is closest to the output of the clock generator where the internal clock signal arrives earliest according to result of the phase comparison.
Preferably, the internal clock generator includes a delay circuit delaying an external clock signal to output the internal clock signal, an output circuit receiving and outputting the internal clock signal, and a circuit controlling delay time of the delay circuit according to a phase difference between an output of the output circuit and the internal clock signal. The correction circuit includes a detection circuit detecting a skew in data output timing between the data output pins, and an adjustment circuit adjusting phase of the output of the output circuit according to an output of the detection circuit.
According to another aspect of the invention, a semiconductor integrated circuit includes a memory cell array having a plurality of memory cells, a plurality of data output pins, a plurality of output buffers provided correspondingly to respective data output pins to
Elms Richard
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Tuan T.
LandOfFree
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