Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-02-01
2003-10-28
Chaudhuri, Olik (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S542000, C257S543000, C438S330000, C438S331000, C438S332000, C438S382000
Reexamination Certificate
active
06639300
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a semiconductor integrated circuit including a resistance region formed on a substrate integrally with an active device and a fabrication process thereof.
Generally, semiconductor devices are provided in the form of a semiconductor integrated circuit in which active devices such as transistors are formed on a substrate monolithically together with passive devices including resistances and/or capacitances.
In the fabrication process of semiconductor integrated circuits, it is preferable that these passive devices are formed simultaneously with the active devices, without increasing the number of the fabrication steps. Further, it is preferable that the active devices are formed with minimum size for maximizing the operational speed thereof.
FIGS. 1A and 1B
are diagrams showing the construction of a compound semiconductor integrated circuit device
10
of a related art in which a hetero-bipolar transistor (HBT) and a cooperating resistance element are integrated, wherein
FIG. 1A
shows the semiconductor integrated circuit in a plan view, while
FIG. 1B
shows the semiconductor integrated circuit in a cross-sectional view taken along a line
1
-
1
′ of FIG.
1
A.
Referring to the cross-sectional view of
FIG. 1B
, it can be seen that a semi-insulating GaAs substrate
11
is provided with a collector layer
11
A of n-type GaAs, and a base layer
12
of thin p-type GaAs is formed epitaxially on the semi-insulating GaAs substrate
11
. Further, an emitter layer
13
of n
+
-type GaInP is formed on the base layer
12
epitaxially.
The substrate
11
is divided into an active device region
10
A and a resistance-element region
10
B by a device-isolation trench
11
B, wherein it can be seen that a device-isolation region
11
C of high resistance is formed inside the device-isolation trench
11
B by an ion implantation process. Thus, the device-isolation trench
11
B thus formed defines the mesa structure for the active device region
10
A and also the mesa structure for the resistance-element region
10
B.
In the active device region
10
A, it should be noted that the emitter layer
13
forms an emitter pattern of a reduced lateral size on the base layer
12
so as to minimize the base-emitter capacitance, and a ring-shaped base electrode
15
A is formed on the surface of the base layer
12
thus exposed as represented in FIG.
1
A. Further, an emitter electrode
14
is formed on the emitter pattern
13
, wherein the emitter electrode
14
extends laterally as a result of the lateral etching process applied to the emitter pattern
13
for reducing the size, and hence the area, thereof. Thereby, the emitter electrode
14
forms an overhang structure on the emitter pattern
13
.
On the resistance-element region
10
B, on the other hand, electrodes
15
C and
15
D are formed on the same base layer
12
. Thereby, there is formed a resistance element having a resistor body provided by the base layer
12
and the electrodes
15
C and
15
D as terminals. In the description hereinafter, the resistance element thus formed in the region
10
B will be designated also by a numeral
10
B. Similarly, the HBT formed on the active region
10
A will be designated also by a numeral
10
A.
In such a semiconductor integrated circuit of
FIGS. 1A and 1B
, it is preferable to form the resistance element and the active device simultaneously by a common process. Thus, there is proposed a process to form the base electrode
15
A of the HBT
10
A and the electrodes
15
C and
15
D of the resistance element
10
B simultaneously.
In more detail, deposition of a conductive layer constituting the base electrode
15
A is made on the active device region
10
A while using the emitter electrode
14
as a mask, after the step of forming the emitter pattern
13
on the base layer
12
and after the step of forming the emitter electrode. As a result of the deposition of the conductive layer thus conducted while using the emitter electrode
14
as a self-alignment mask, an electrode pattern
15
B of the same composition as the base electrode
15
A is formed also on the emitter electrode
14
.
As a result of the deposition of the conductive layer, the electrodes
15
C and
15
D are formed at the same time, as noted previously. In view of the fact that the electrodes
15
C and
15
D are used as the different terminals of the resistance element, it is necessary that the electrodes
15
C and
15
D are isolated from each other, and thus, it has been necessary to apply a patterning process using a mask for forming the electrodes
15
C and
15
D.
In view of the circumstances noted above, it has been necessary to use a mask having mask openings P
1
-P
3
corresponding respectively to the electrode patterns
15
A,
15
C and
15
D as represented in
FIG. 2A
for patterning the electrodes
15
C and
15
D, while no such a mask is actually needed for patterning the base electrode
15
A. It should be noted that the emitter electrode
14
can be used as a self-aligned mask during the process of forming base electrode
15
A of the HBT
10
A.
In the fabrication process of the semiconductor integrated circuit
10
of the related art, it should be noted that another mask process, using a mask pattern having mask openings Q
1
and Q
2
respectively corresponding to the mesa region
10
A and the mesa region
10
B represented in
FIG. 2B
, is necessary for forming the device isolation trench
11
B.
Thus, the fabrication process of the semiconductor integrated circuit
10
of the related art includes two different mask processes, one using the mask pattern of
FIG. 2A
for forming the electrodes
15
A,
15
C and
15
D, and the other using the mask pattern of
FIG. 2B
for forming the mesa regions
10
A and
10
B.
In such a process that uses two different mask processes, there inevitably arises the problem of mask misalignment. Thus, in order to tolerate possible mask misalignment, it has been necessary to secure a sufficiently large area for the mesa regions
10
A and
10
B, while such an increase of the mesa area invites unwanted increase of parasitic capacitance and resultant decrease of the operational speed of the HBT. In
FIGS. 1A and 1B
it should be noted that the drawings represent resist patterns
16
A and
16
B that are formed by the mask pattern of
FIG. 2B
, wherein the resist pattern
16
A corresponds to the resist opening Q
1
while the resist pattern
16
B corresponds to the resist opening Q
2
.
The foregoing problem of increased parasitic capacitance of HBT may be eliminated when a self-alignment mask similar to that used for the active device region
10
A is provided also in the resistance-element region
10
B and make the electrodes
15
C and
15
D separate as a result of use of such a self-alignment mask. In this case, the mask process for patterning the electrodes
15
C and
15
D by using the mask of
FIG. 2A
can be omitted. Thus, when successful, such a process would minimize the area of the HBT
10
A and simultaneously simplify the fabrication process of the semiconductor integrated circuit
10
.
FIGS. 3A-3C
represents the case of fabricating a semiconductor integrated circuit device by using a self-alignment mask also in the resistance-element region
10
B according to the foregoing approach. It should be noted that
FIGS. 3A-3C
merely represent one possible option of eliminating the problem pertinent to the fabrication process of the semiconductor integrated circuit
10
of
FIGS. 1A and 1B
and does not represent a known or prior art process. In
FIGS. 3A-3C
, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to
FIGS. 3A and 3B
, it can be seen that the resistance-element region
10
B of the semiconductor integrated circuit
10
now includes a dummy emitter region
13
A having a reduced lateral size, and a dummy-emitter electrode
14
A corresponding to the emitter electrode
1
Berezny Neal
Chaudhuri Olik
Fujitsu Quantum Devices Limited
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