Semiconductor integrated circuit having a scan circuit provided

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

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324 731, 371 223, G01R 3128, G06F 1100

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active

053410963

ABSTRACT:
A semiconductor integrated circuit device in which a scan circuit is self-contained, is adapted to implement a dynamic burn-in test within an LSI device. The device includes an internal circuit provided in an LSI chip; a scan circuit for delivering scan data into the internal circuit; scan data generation circuit for generating scan data corresponding to a test mode signal; and a clock generation circuit for generating scan clocks corresponding to the test mode signal. In the internal circuit, the scan circuit, the scan data generation circuit and the clock generation circuit are arranged in the LSI chip. Corresponding to the test mode signal, data produced by the scan data generation circuit is delivered to the scan circuit.

REFERENCES:
patent: 4278897 (1981-07-01), Ohno et al.
patent: 4894830 (1990-01-01), Kawai
patent: 4912395 (1990-03-01), Sato et al.
"Tab Design With Burn-in Feature", IBM Technical Disclosure Bulletin, 700, vol. 31, No. 5, Oct. 1988.
"Technique For a Dynamic Burn-in Test", IBM Technical Disclosure Bulletin, vol. 32, No. 8B, Jan. 1990.
"A Fully Integrated Design Methodology for 100K-Gate CMOS Custom LSIs With Tab Packaging", IEEE 1989 Custom Integrated Circuits Conference.
"Design For Testability and Built-in Self Test: A Review", IEEE Transactions of Industrial Electronics, vol. 36, No. 2, May 1989.
"Digital Logic Testing and Simulation", Alexander Miczo, 1986, Harper & Row, Publishers, Inc., New York, pp. 276-280.

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