Semiconductor integrated circuit having a plurality of oscillati

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364DIG2, 364934, 3649342, 3649344, 364950, 3649504, 3649505, G06F 104

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052610829

ABSTRACT:
Operation of a clock generating circuit is stopped when the oscillation signals to be selectively transmitted to the clock generating circuit via a multiplexer are switched. The oscillation signals are generated by a first oscillation circuit at a relatively high frequency and by a second oscillation circuit which steadily oscillates at a relatively low frequency. The clock generating operation is resumed in synchronization with the switched oscillation signals.

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patent: 4464584 (1984-08-01), Hentzschel et al.
patent: 4615005 (1986-09-01), Maejima et al.

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