Communications: electrical – Digital comparator systems
Patent
1997-08-06
1999-04-13
Callahan, Timothy P.
Communications: electrical
Digital comparator systems
327199, G05B 1007
Patent
active
058942130
ABSTRACT:
A semiconductor integrated circuit is activated to allow a plurality of FFs 1 incorporated therein to latch data therein. Thereafter, the semiconductor integrated circuit is switched to test mode connections. Upon the test mode connections, for example, FFs are connected in plural stages to form scan paths 101 through 10m and scan paths 111 through 11m paired up therewith. When expected values corresponding to data latched in the scan paths 101 through 10m of the other of the pair are written into the scan paths 111 through 11m of one of the pair, respectively and they are shift-operated, exclusive OR circuits 121 through 12m successively compare the latched data and the expected values. Further, an OR circuit 13 successively outputs data indicative of whether or not the semiconductor integrated circuit works normally. Insofar as the latched data and the expected values coincide with each other, the OR circuit 13 outputs "0".
REFERENCES:
patent: 4064488 (1977-12-01), Chapman
patent: 4246569 (1981-01-01), Baldwin et al.
patent: 5245311 (1993-09-01), Honna
patent: 5398270 (1995-03-01), Cho et al.
patent: 5578938 (1996-11-01), Kazami
Callahan Timothy P.
Nguyen Hai L.
OKI Electric Industry Co., Ltd.
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