Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1997-04-28
2001-07-10
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S158000, C327S159000
Reexamination Certificate
active
06259288
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a DLL (Delay Locked Loop) circuit and a special power supply circuit for the DLL circuit.
2. Description of the Related Art
Recently, an operation speed of a semiconductor integrated circuit has been increased, and a circuit scale thereof has become large. Further, it has been necessary to supply a synchronized signal (phase synchronized clock signal) to a specific circuit in a large scale semiconductor integrated circuit.
For example, an operation speed of a memory device, e.g., a synchronous DRAM (SDRAM), now exceeds 100 MHz, and a DLL circuit must be used to synchronize a signal with an external clock and supply the synchronized signal to a plurality of output buffers, so as to remove a delay of an internal clock. Namely, a phase of the external clock is coincident with that of the internal clock, and thereby a delay or fluctuation of an access time is removed.
Specifically, in a SDRAM, a DLL circuit must be used to synchronize an internal clock with an external clock and supply the synchronized internal clock to a plurality of output buffers, so as to remove a delay of an internal clock. Namely, a phase of the external clock is coincident with that of the internal clock, and thereby a delay or fluctuation of an access time is removed. Further, in accordance with increasing the operation speed of the semiconductor integrated circuit, the internal clock generated by the DLL circuit should have much higher accuracy.
In a semiconductor integrated circuit of a related art, a DLL circuit and peripheral circuits except for the DLL circuit commonly receive the same power supply voltage output from a power supply circuit. Therefore, when the peripheral circuits use a large current from the power supply circuit or when noise is caused in the power supply voltage in an area of the peripheral circuits, the power supply voltage applied to the DLL circuit is lowered or fluctuated by the noise, and the internal clock output from the DLL circuit is not stable and the accuracy (synchronization with the external clock) of the internal clock is decreased. In addition, the internal clock output from the DLL circuit may include a jitter.
The related arts and their associated problems will be described in detail later with reference to the accompanying drawings.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit having a DLL circuit which can generate an internal clock being stable and accurately synchronized with an external clock without including a jitter.
According to the present invention, there is provided a semiconductor integrated circuit having a DLL circuit for receiving a first control signal and generating a second control signal synchronized with the first control signal by carrying out a phase synchronization process, comprising a power supply circuit for supplying a power supply voltage only to the DLL circuit.
Further, according to the present invention, there is provided a semiconductor integrated circuit comprising a DLL circuit for receiving a first control signal and generating a second control signal synchronized with the first control signal by carrying out a phase synchronization process; a first power supply circuit for supplying a power supply voltage to the DLL circuit; peripheral circuits except for the DLL circuit; and a second power supply circuit for supplying a power supply voltage to the peripheral circuits.
The first power supply circuit may be a voltage down generator. The voltage down generator may comprise a transistor having a source to which a power supply voltage of the semiconductor integrated circuit is applied, a gate to which a control voltage is applied, and a drain through which an output voltage of the voltage down generator is applied to the DLL circuit. The voltage down generator may further comprise a capacitor for maintaining the control voltage applied to the gate of the transistor.
The DLL circuit may comprise a first delay circuit for receiving the first control signal and supplying the second control signal having a specific delay to an object circuit; a divider circuit for receiving the first control signal; a second delay circuit for receiving a first output signal of the divider circuit; a phase comparator having a first input to which a second output signal of the divider circuit is supplied and a second input to which an output signal of the second delay circuit is supplied through a delay applying unit, for carrying out a comparing process of comparing the phases of the second output signal of the divider circuit and the output signal of the second delay circuit, the delay applying unit applying a delay corresponding to a time determined by transferring an output signal of the first delay circuit from the first delay circuit to the object circuit; and a delay controller for receiving an output signal of the phase comparator and controlling delay values of the first and second delay circuits.
The divider circuit may generate the first and second output signals by X-dividing a frequency of the first control signal, and the comparing process of the phase comparator may be carried out by every X periods of the first control signal, where X denotes an integer number of two or more. The first and second output signals of the divider circuit may be complementary signals. The divider circuit may generate the first signal where Y periods of the first control signal is at a first level and Z periods of the first control signal is at a second level, and the comparing process of the phase comparator may be carried out at a timing of delaying Y periods of the first control signal, where Y denotes an integer number of two or more, and Z denotes an integer number.
The first control signal may be supplied through an input circuit, and the output signal of the second delay circuit may be supplied to the second input of the phase comparator through the dummy line, a dummy object circuit, and a dummy input circuit. A sum of a delay of the input circuit, a minimum delay of the first delay circuit, a delay of the dummy line, and a delay of the object circuit may exceed one period of the first control signal, the comparing process of the phase comparator may be carried out by a timing of delaying two or more periods of the first control signal. The semiconductor integrated circuit may be a synchronous DRAM, and the object circuit may be an output circuit of the synchronous DRAM.
REFERENCES:
patent: 3961282 (1976-06-01), Chen et al.
patent: 4338569 (1982-07-01), Petrich
patent: 4922141 (1990-05-01), Lofgren et al.
patent: 5049766 (1991-09-01), Van Driest et al.
patent: 5087829 (1992-02-01), Ishibashi et al.
patent: 5117205 (1992-05-01), Nauta
patent: 5124796 (1992-06-01), Maki
patent: 5218244 (1993-06-01), Nokubo
patent: 5223755 (1993-06-01), Richley
patent: 5440515 (1995-08-01), Chang et al.
patent: 5610543 (1997-03-01), Chang et al.
patent: 5619166 (1997-04-01), Gross
patent: 5642082 (1997-06-01), Jefferson
patent: 5684421 (1997-11-01), Chapman et al.
patent: 5686868 (1997-11-01), Hasegawa et al.
patent: 5687202 (1997-11-01), Eitrheim
patent: 5731735 (1998-03-01), Yokota et al.
patent: 5764092 (1998-06-01), Wada et al.
patent: 5796673 (1998-08-01), Foss et al.
patent: 5990715 (1999-11-01), Nishimura
Arent Fox Kintnerr Plotkin & Kahn, PLLC
Callahan Timothy P.
Fujitsu Limited
Luu An
LandOfFree
Semiconductor integrated circuit having a DLL circuit and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit having a DLL circuit and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit having a DLL circuit and a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2567755