Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2007-09-06
2009-10-06
Patel, Paresh (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
07598761
ABSTRACT:
It is made possible to detect degradation in a circuit before an operation fault will occur. A semiconductor integrated circuit includes: a circuit to be tested; a plurality of logical circuits which have different logical thresholds and which perform operation on an output of the circuit to be tested, on the basis of the logical thresholds; and a degradation notice signal generation circuit which generates a degradation notice signal to give notice that the circuit to be tested has degraded, when outputs of the logical circuits do not coincide with each other.
REFERENCES:
patent: 4853628 (1989-08-01), Gouldsberry et al.
patent: 5742177 (1998-04-01), Kalb, Jr.
patent: 5870623 (1999-02-01), Shirata
patent: 6145107 (2000-11-01), Farokhzad
patent: 6550038 (2003-04-01), Shirata
patent: 7102358 (2006-09-01), Keshavarzi et al.
patent: 7116110 (2006-10-01), Li
patent: 2008/0035921 (2008-02-01), Gonzalez et al.
patent: 2009/0082978 (2009-03-01), Yang et al.
patent: 62-145173 (1987-06-01), None
patent: 9-197021 (1997-07-01), None
patent: 10-78920 (1998-03-01), None
patent: 10-133900 (1998-05-01), None
patent: 2003-177935 (2003-06-01), None
patent: 2006-60690 (2006-03-01), None
patent: 2008066536 (2008-03-01), None
Dehon, “Array-Based Architecture for FET-Based, Nanoscale Electronics,” IEEE Transactions on Nanotechnology (Mar. 2003), 2:23-32 ( 10 pages).
Notification of Reasons for Rejection issued by the Japanese Patent Office on Feb. 24, 2009, for Japanese Patent Application No. 2006-243290, and English-language translation thereof.
Notification of Reasons for Rejection issued by the Japanese Patent Office on Oct. 31, 2008, for Japanese Patent Application No. 2006-243290, and English-language translation thereof.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Patel Paresh
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