Semiconductor integrated circuit having a decoding and level shi

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307451, 307475, 307448, H03K 19094, H03K 19017, H03K 17687, H03K 1704

Patent

active

050197274

ABSTRACT:
A decoding and level shifting circuit comprises first and second n-channel transistors each having a source connected to a high negative potential, a gate and a drain of the first n-channel transistor being connected to a drain and a gate of the second n-channel transistor, respectively. A first group of p-channel transistors are connected in parallel between the drain of the first n-channel transistor and a ground level, and gates of the first group of p-channel transistors are connected to receive a first group of signals, respectively. A second group of p-channel transistors are connected in series between the drain of the second n-channel transistor and the ground level, and gates of the second group of p-channel transistors are connected to respectively receive a second group of signals complementary to the first group of signals. The drain of the second n-channel transistor gives an output.

REFERENCES:
patent: 4581548 (1986-04-01), Young
patent: 4620116 (1986-10-01), Ozawa
patent: 4798977 (1989-01-01), Sakui et al.
patent: 4866305 (1989-09-01), Hasegawa

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