Semiconductor integrated circuit having a C-MOS internal logic b

Details Semiconductor integrated circuit having a C-MOS internal logic b Semiconductor integrated circuit having a C-MOS internal logic b

1984-08-31

1987-02-24

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307455, 307475, 307497, H03K 1712, H03K 1901

Patent

active

046459510

ABSTRACT:
A semiconductor integrated circuit is provided which combines an MOS internal logic circuit (C-MOS in the preferred embodiment) with input and output buffers which have pin-compatibility with ECL circuitry. An ECL-CMOS level-conversion input buffer circuit arranged for a C-MOS internal logic circuit has a pair of emitter-coupled transistors which are responsive to an input signal at an ECL level. Thus, the input buffer circuit operates at a high speed. A CMOS-ECL level-conversion output buffer circuit arranged for the C-MOS internal logic circuit has an amplifying transistor, which has its base responsive to the output signal of the C-MOS internal logic circuit, and an emitter-follower transistor which has its base responsive to the collector signal of said amplifying transistor for generating an output signal at an ECL level at its emitter. Thus, the output buffer circuit operates at a high speed. Utilizing such an arrangement, the circuit can obtain the benefits of lower power consumption for the C-MOS internal logic circuit together with high speed in the buffer stages and ECL compatibility.

REFERENCES:
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patent: 4450371 (1984-05-01), Bismarck
patent: 4453095 (1984-06-01), Wrathall
patent: 4472647 (1984-09-01), Allgood et al.
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patent: 4527079 (1985-07-01), Thompson
patent: 4563601 (1986-01-01), Asano et al.
Clemen et al, "V.sub.T -Compensated TTL-Compatible MOS Amplifier", IBM T.D.B., vol. 21, No. 7, 12-1978, pp. 2874-2875.

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