Semiconductor integrated circuit for phase management of...

Details Semiconductor integrated circuit for phase management of... Semiconductor integrated circuit for phase management of...

2005-03-01

2005-03-01

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

06861883

ABSTRACT:
Assuming that clocks in an A clock driver (102), a B clock driver (103) and a CMOS buffer circuit (119) have delay values Ta, Tb and Td, respectively, a delay value Ta−Td is stored in a register circuit (117) when terminals “0” of selector circuits (114, 115, 116) are selected, and a delay value Ta−Td−Tb is stored in a register circuit (118) when the terminals “0” are switched to “1”. Thus, determining a delay value at the CMOS buffer circuit (119) allows a phase difference between the A clock driver (102) and B clock driver (103) to be determined.

REFERENCES:
patent: 4689581 (1987-08-01), Talbot
patent: 5081428 (1992-01-01), Atriss et al.
patent: 5270592 (1993-12-01), Takahashi et al.
patent: 5815540 (1998-09-01), Aoki
patent: 6346830 (2002-02-01), Ishikawa
Albert Thaik, et al., “A Dual PLL Based Multi Frequency Clock Distribution Scheme”, 1992 Symposium on VLSI Circuits Digest of Technical Papers, 1992, pp. 84-85.

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