Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
1999-11-09
2001-10-02
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S112000, C326S080000
Reexamination Certificate
active
06297674
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and particularly to a semiconductor integrated circuit using MOS transistors.
In recent years, high integration and low power consumption have been promoted in various kinds of semiconductor integrated circuits. In a semiconductor integrated circuit, there is a threshold voltage Vt for determining the on-off characteristic of an MOS transistor. The threshold voltage Vt must be lowered to improve drivability to thereby improve the operating speed of the circuit. Even in the case where the internal supply voltage Vdd of the circuit is lowered, the threshold voltage Vt needs to be set to be small in order to keep the operating speed high.
Lowering of the threshold voltage Vt, however, incurs a problem that the power consumption of the semiconductor integrated circuit increases greatly due to rapid increase of leakage current as described in 1993 Symposium on VLSI Circuits Digest of Technical Papers, pp. 45-46.
To prevent this problem, there is proposed a semiconductor integrated circuit in which the substrate bias voltage is changed according to the operating mode, such as a stand-by mode, an active mode, or the like, to thereby control the threshold voltage of an MOS transistor, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 166-167, 1996.
On the other hand, there is a further proposal in which real and virtual power supply lines are provided so as to be linked by switching MOS transistors so that main circuits are supplied with power through the virtual power supply lines but the switching MOS transistors are turned off in the stand-by mode to prevent the main circuits from being supplied with power to thereby achieve reduction of power consumption, in IEEE Journal of Solid-State Circuits, Vol. 30, No. 8, August 1995. Increase of the leakage current is, however, unavoidable for high-speed operation in the active mode even in the case where these background-art techniques are used.
FIGS. 24A and 24B
show three stages of inverters as an example of background-art circuit.
FIG. 24A
shows an equivalent circuit configuration.
FIG. 24B
shows a specific circuit configuration. When, for example, node O
1
is at an “L” level in the stand-by mode, node O
3
is at an “L” level and nodes O
2
and O
4
are at an “H” level. In this case, with respect to the first and second stages of inverters, a leakage current flows through transistors Q
1
and Q
4
. If the threshold voltage of the transistors is lowered, the leakage current increases greatly.
On the other hand, in accordance with JP-A-7-162288, there is a proposal in which time difference is provided between a signal supplied to an MOS transistor changed from OFF to ON and a signal supplied to an MOS transistor changed from ON to OFF so that the former signal is propagated earlier than the latter signal to thereby achieve high-speed operation without providing any change of the threshold voltage Vt. If the former signal is propagated earlier, it is, however, impossible to expect a greatly speeding-up effect as a whole because the latter signal is propagated later. The inventors' examination has proved that the speeding-up effect is about 10% at the best.
In each of the background-art semiconductor integrated circuits, as described above, there was a problem that the leakage current in the active mode increased when the operating speed of the circuit was improved or kept high even when the internal supply voltage Vdd was lowered.
SUMMARY OF THE INVENTION
The present invention is configured in consideration of the aforementioned circumstances and it is an object thereof to provide a semiconductor integrated circuit in which not only power consumption caused by a leakage current in an active mode can be suppressed from increasing but also the circuit can operate at a high speed.
In order to achieve the above object, according to an aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a first p-channel FET having a gate controlled by a first input and having a source-drain path connected between a first operating potential point and a first node; a first n-channel FET having a gate controlled by a second input and having a source-drain path connected between the first node and a second node; a second n-channel FET having a gate controlled by the first node and having a source-drain path connected between the second node and a second operating potential point; a third n-channel FET having a gate controlled by the first node and having a source-drain path connected between the second node and a third operating potential point; a second p-channel FET having a gate controlled by the first input and having a source-drain path connected between a third node and a fourth node; a third p-channel FET having a gate controlled by the fourth node and having a source-drain path connected between the first operating potential point and the third node; a fourth p-channel FET having a gate controlled by the fourth node and having a source-drain path connected between a fourth operating potential point and the third node; and a fourth n-channel FET having a gate controlled by the second input and having a source-drain path connected between the fourth node and the second operating potential point.
According to another aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a first p-channel FET having a gate controlled by a first input and having a source-drain path connected between a first operating potential point and a first node; a first n-channel FET having a gate controlled by a second input and having a source-drain path connected between the first node and a second operating potential point; a second n-channel FET having a gate controlled by the first operating potential point and having a source-drain path connected between the first node and the second operating potential point; a second p-channel FET having a gate controlled by the first node and having a source-drain path connected between the first operating potential point and the second node; a third n-channel FET having a gate controlled by the second input and having a source-drain path connected between the second node and the second operating potential point; and a third p-channel FET having a gate controlled by the second operating potential point and having a source-drain path connected between the first operating potential point and the second node.
According to a further aspect of the present invention, in view of the operation of an input signal, there is provided a semiconductor integrated circuit comprising a PMOS transistor (or a p-channel FET) and an NMOS transistor (an n-channel FET), wherein: a first signal is supplied to a gate of the PMOS transistor; a second signal is supplied to a gate of the NMOS transistor; and the first signal and the second signal are different from each other and satisfy the relations
PS≦NS<PL≦NL
in which PL is the largest level of the first signal, PS is the smallest level of the first signal, NL is the largest level of the second signal, and NS is the smallest level of the second signal.
According to a further aspect of the present invention, there is provided a semiconductor integrated circuit comprising a PMOS transistor, and an NMOS transistor, wherein: a first signal is supplied to a gate of the PMOS transistor; a second signal is supplied to a gate of the NMOS transistor; and the first signal and the second signal are different from each other and levels PS, NS, NG, PG, PL and NL are arranged in order when the first signal changes between PL and PS, the second signal changes between NL and NS, PG is a gate input level serving as a threshold for turning on/off the PMOS transistor, and NG is a gate input level serving as a threshold for turning on/off the NMOS transistor.
Here, preferably, the difference between NG and NL is larger than the difference between NG and NS. Further, preferably, the difference betwee
Kato Naoki
Kono Ichiro
Yano Kazuo
Cunningham Terry D.
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Tra Quan
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