Semiconductor integrated circuit for interfacing I.sup.2 L with

Details Semiconductor integrated circuit for interfacing I.sup.2 L with Semiconductor integrated circuit for interfacing I.sup.2 L with

1981-09-02

1984-09-11

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307477, H03K 19091, H03K 19092

Patent

active

044712413

ABSTRACT:
A semiconductor integrated circuit comprising an integrated injection logic circuit, a peripheral circuit driven by a high-voltage power source, and an interface circuit disposed between the integrated injection logic circuit and the peripheral circuit.
The interface circuit is connected with a reference power source. At the output terminal of the integrated injection logic circuit appears such voltage that the collector-emitter voltage of an output transistor of the integrated injection logic circuit is lower than the collector-emitter breakdown voltage (base open) of the output transistor. Further, the interface circuit has a withstanding voltage higher than the collector-emitter breakdown voltage of the output transistor of the integrated injection logic circuit.

REFERENCES:
patent: 3610949 (1971-10-01), Armgarth
patent: 3798471 (1974-03-01), Williams et al.
patent: 4100431 (1978-07-01), Stipanuk
patent: 4158146 (1979-06-01), Smeulers et al.
patent: 4256984 (1981-03-01), Kojima
patent: 4358689 (1982-11-01), Jarrett et al.
patent: 4366397 (1982-12-01), Kitamura et al.
patent: 4390802 (1983-06-01), Woltz
Lsaelius, "Simple Circuit Interfaces TTL to CMOS with Single 12-V Supply," Electronic Design 25, 12/6/76, p. 313.
Petrie et al., "Stacked I.sup.2 L Structures", IEEE Journal of Solid State Circuits, vol. SC-15, No. 2, Apr. 1980.
Jenkins, "Interface Circuits Drive High-Level Switches from Low-Level Inputs", Electronic Engineering, May 1971, pp. 45-49.
Japanese Patent Disclosure (Kokai), No. 54-158157, R. Martin; Dec. 13, 1979, Texas Instruments Inc.

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