Semiconductor integrated circuit for holding an output...

Details Semiconductor integrated circuit for holding an output... Semiconductor integrated circuit for holding an output...

2002-07-15

2004-04-27

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S544000

Reexamination Certificate

active

06727743

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit.
A semiconductor integrated circuit of
FIG. 1
is conventionally proposed in order to reduce current consumption in the non-operating state of the semiconductor integrated circuit. Hereinafter, this semiconductor integrated circuit will be described.
Referring to
FIG. 1
, a PMOS (P-channel Metal Oxide Semiconductor) transistor
4
(hereinafter, simply referred to as “PMOS”) is connected between a power supply terminal
2
of an inverter circuit
1
and a power supply potential
7
. An NMOS (N-channel Metal Oxide Semiconductor) transistor
5
(hereinafter, simply referred to as “NMOS”) is connected between a ground terminal
3
of the inverter circuit
1
and a ground potential
8
. These transistors are manufactured with a greater threshold value (absolute value) than transistors in the inverter circuit
1
. Therefore, when the inverter circuit
1
is in the non-operating state, the PMOS
4
and the NMOS
5
are turned OFF as shown in the figure. As a result, a current flowing into the inverter circuit
1
is limited by these transistors and the like, enabling reduction in current consumption in the non-operating state.
However, when PMOS
4
and the NMOS
5
are turned OFF, the inverter circuit
1
is rendered in a substantially open state as viewed from the power supply potential
7
and the ground potential
8
of the power supply terminal
2
and the ground terminal
3
. Therefore, regardless of the potential of an input signal
6
, the power supply terminal
2
and the ground terminal
3
transition toward the same potential by the current in the inverter circuit
1
, and finally reach the same potential. As a result, the conventional semiconductor integrated circuit reduces current consumption in the non-operating state, but cannot hold a signal that is determined at an output terminal
9
in the operating state.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor integrated circuit capable of reducing current consumption in the non-operating state and holding, even in the non-operating state, a signal determined in the operating state.
In order to achieve the above object, the present invention is made based on the following considerations: first, how an output signal is determined in the operating state of the semiconductor integrated circuit will be described. Thereafter, in what state the active elements of the circuit are required to be in order to hold the output signal determined in the operating state even in the non-operating state of the semiconductor integrated circuit will be described. Thereafter, the problems will be described which are encountered when the output signal determined in the operating state is held when the power supply potential is set to an extremely low value (a value that is commonly recognized to be too low to operate the transistors due to an extremely small operating current (at most several tens of nanoamperes)), as shown in
FIGS. 4A
,
4
B. For example, the extremely low potential is a potential equal to or lower than a threshold value Vt (absolute value) of the transistors. Basic technology for solving such problems will also be described. The following discussion is given for an inverter circuit formed from a PMOS and an NMOS, a basic structure of the logic circuit.
FIG. 2A
shows an inverter circuit formed from a PMOS
10
and an NMOS
11
. State transition of the PMOS
10
and the NMOS
11
will be considered. It is herein assumed that a signal applied from a signal generator
13
to an input terminal
12
of the inverter circuit transitions from L level (ground potential level) to H level (power supply potential level). As shown in “Initial State” in Table 1 below, a current In of the NMOS
11
(a current flowing from the drain terminal to the source terminal) is sufficiently greater than a current Ip of the PMOS
10
(a current flowing from the source terminal to the drain terminal) right after the input signal transitions from L level to H level. The power supply terminal as considered herein refers to a power supply potential that allows the inverter circuit to achieve a desired design operating speed in the operating state. The current In of the NMOS
11
is about a hundred times as large as the current Ip of the PMOS
10
. Therefore, such a state is commonly described like “the NMOS
11
is ON and the PMOS
10
is OFF”.
TABLE 1
Input Signal
Initial State
Final State
Output Signal
L → H
Ip << In
Ip = In
H → L
Rp >> Rn, (Gp << Gn)
H → L
Ip >> In
Ip = In
L → H
Rp << Rn, (Gp >> Gn)
Since Ip<<In in the initial state, a current flows out of a load capacitor
14
. As a result, a connection terminal with the inverter circuit falls toward the ground potential, and finally reaches the final state in Table 1. In the final state, Ip is equal to In, and an output terminal of the inverter circuit is at L level. The reason why the output terminal transitions to L level is that a resistance value Rp from the source terminal to the drain terminal of the PMOS
10
is greater than a resistance value Rn from the drain terminal to the source terminal of the NMOS
11
. Therefore, the output signal Vout
1
in the final state is given by the following expression:
V
out1
=Rn
/(
Rp+Rn
)
Vdd
1→0  (1).
In other words, the output signal Vout
1
transitions to L level in the final state. In the expression (1), Vdd
1
is a first power supply potential, and Rn/Rp is approximated to zero. The output signal in the final state is thus determined by the resistance values Rp, Rn of the PMOS
10
and the NMOS
11
. Hereinafter, considerations will be given by commonly used terms and expressions. Therefore, conductances Gp, Gn of the PMOS
10
and the NMOS
11
(the reciprocals of the resistance values Rp, Rn: 1/Rp, 1/Rn) are used instead of the resistance values Rp, Rn. The above description is given for the case where the input signal transitions from L level to H level. Table 1 also shows the initial state and the final state regarding transition from H level to L level. Since operation is the same as that described above, description thereof will be omitted.
Hereinafter, the meaning of the expression “the output signal is lost” will be described.
FIGS. 3A
to
3
F and
FIGS. 4A
,
4
B show characteristics of the PMOS and the NMOS. In the figures, the abscissa indicates a voltage Vds between the drain terminal and the source terminal of the PMOS and the NMOS, and the ordinate indicates a current Id between the drain terminal and the source terminal of the PMOS and the NMOS. In order to show the characteristics of the PMOS and the NMOS in the first quadrant of the graph, the graphs were written on the following conditions: for the PMOS, the abscissa indicates a potential of the source terminal relative to the drain terminal and the ordinate indicates a current flowing from the source terminal to the drain terminal; and for the NMOS, the abscissa indicates a potential of the drain terminal relative to the source terminal and the ordinate indicates a current flowing from the drain terminal to the source terminal. The same applies to
FIGS. 5A
,
5
B,
7
and
10
in order to show the characteristics of the PMOS and the NMOS in the first quadrant of the graph.
Curve Non in
FIG. 3C
represents current characteristics of the NMOS in the state of FIG.
3
A. The gate terminal of the NMOS is connected to the drain terminal thereof. As shown by thick line in
FIG. 3C
, the current characteristics of the NMOS exhibit a profile close to a quadratic curve with decrease in voltage Vds on the abscissa. Curves Noff represent characteristics of the NMOS in the state of FIG.
3
B. It is herein assumed that different fixed potentials Vg (i.e., Vg
1
, Vg
2
, Vg
3
) are applied to the gate terminal of the NMOS (Vg
1
>Vg
2
>Vg
3
). Each curve A, B, C of the current characteristics Noff has the same property. More specifically, provide

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit for holding an output... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit for holding an output..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit for holding an output... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3212252