Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2011-03-15
2011-03-15
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S193000, C365S233100, C365S233170, C365S236000
Reexamination Certificate
active
07907472
ABSTRACT:
A semiconductor integrated circuit (100) fetches read data from DDR-SDRAMs (110, 120) each operating in synchronization with a clock, and transfers the read data. The semiconductor integrated circuit (100) includes read buffers (104, 105) for fetching the read data from the DDR-SDRAMs (110, 120), and transferring the read data, latch timing control circuits (102, 103) for controlling respective latch timings with which the read buffers (104, 105) fetch the read data from the DDR-SDRAMs (110, 120) based on respective data strobe signals from the DDR-SDRAMs (110, 120), and a read timing control circuit (106) for controlling respective read timings with which the read buffers (104, 105) transfer the read data based on the latch timings of the latch timing control circuits (102, 103).
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Fukumoto Satoshi
Kogishi Toshiya
Ho Hoai V
McDermott Will & Emery LLP
Panasonic Corporation
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