Telecommunications – Transmitter and receiver at same station – Radiotelephone equipment detail
Reexamination Certificate
2000-02-14
2002-06-18
Hunter, Daniel (Department: 2684)
Telecommunications
Transmitter and receiver at same station
Radiotelephone equipment detail
C455S136000, C455S138000
Reexamination Certificate
active
06408195
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit (hereinafter referred to as an IC) in which a protocol decoding function and a micro-controller function, which are used for a serial data receiving device typified by a wireless call device (hereinafter referred to as a pager), are integrated.
Also, the present invention relates to an IC having a communication protocol decoding function used for a serial data receiving device typified by a pager or the like.
Further, the present invention relates to an IC having a protocol decoding function used for a serial data receiving device typified by a pager or the like and a method of saving a battery thereof.
BACKGROUND ART
A portable serial data receiving device, used as a pager or the like, having a block structure as shown in
FIG. 2
is conventionally used. This receiving device includes a system clock generating circuit
4
for generating timing signals on receiving an output of an oscillating circuit
1
, a data receiving circuit
3
for synchronously making entry of data inputted through a serial data input terminal C on receiving the clock output, and for checking an ID and detecting and correcting an error for the entered data, that is, the data receiving circuit having a so-called protocol decoding function, and a micro-controller circuit
69
for controlling the data receiving circuit
3
on receiving the clock from the system clock generating circuit
4
, for making entry of the received data to process the data, and at the same time, for informing the outside of the reception.
A resonator (normally crystal resonator) is connected between input and output terminals A and B of the oscillating circuit
1
. The oscillation output is used as a reference clock for synchronization of the data receiving circuit
3
and for operating a processing circuit. Also, the oscillation output is inputted into the system clock generating circuit
4
and is converted into a system clock necessary for the operation of the micro-controller circuit
69
.
A pager as an example will be described. In
FIG. 2
, data inputted through the data input terminal C is entered in the data receiving circuit
3
. At that time, synchronization is made by using the output of the oscillating circuit
1
. When the data receiving circuit
3
confirms the data reception by checking the ID, it requests interruption of the micro-controller circuit
69
, and starts to make entry of the data. The entered data is entered into the micro-controller circuit
69
which has started its operation by receiving the interruption request, and is stored or displayed as occasion demands. The micro-controller circuit
69
is also provided with an output terminal D through which an alarm sound is given to the outside at the data reception or an LED is turned on, so that it outputs an alarm signal as occasion demands.
In this way, data processing is executed. However, in the structure shown in
FIG. 2
, since the output of the oscillating circuit
1
is connected to both the data receiving circuit
3
and the system clock generating circuit
4
, as a data rate becomes fast, a processing time of the micro-controller is required to be shortened.
FIG. 3
shows another prior art in which two oscillating circuits are included. The respective outputs of oscillating circuits
1
and
67
are inputted into a clock switching circuit
68
. The clock switching circuit
68
is controlled by a control signal G of the micro-controller circuit
69
, and the output thereof is inputted into the system clock generating circuit
4
. Since other components are common to those of the example shown in
FIG. 2
, they are designated by similar reference numerals or symbols and the description thereof will be omitted. In the circuit shown in
FIG. 3
, in the case where a processing speed of the micro-controller circuit
69
is insufficient, the oscillating frequency of the oscillating circuit
67
is increased and a clock is changed as occasion demands, so that the speed of the system clock can be increased.
Also, a portable serial data receiving device, used as a pager or the like, having a block structure as shown in
FIG. 9
is conventionally used. The receiving device includes a frequency dividing circuit
2
for dividing the output of a reference clock generating circuit
17
; a control circuit
18
for generating a control signal on receiving the output of the circuit
2
; a synchronization correcting circuit
5
connected to a data input terminal C and operating with the receipt of a clock from the frequency dividing circuit
2
; an error correcting circuit
6
, a signal detecting circuit
7
and a synchronization code detecting circuit
8
which are operated by receiving the output of the circuit
5
and the outputs of the frequency dividing circuit
2
and the control circuit
18
; an address comparing circuit
9
receiving the output of the frequency dividing circuit
2
and the control circuit
18
and checking the outputs of the error correcting circuit
6
and an address memory circuit
10
; and an input/output control circuit
11
connected to the address memory circuit
10
, receiving the outputs of the control circuit
18
and the error correcting circuit
6
, and connected to an input/output terminal
12
. In
FIG. 9
, all components other than the reference clock generating circuit
17
and the frequency dividing circuit
2
will be collectively referred to as a data receiving circuit
3
.
FIGS. 10 and 11
show a conventional structure of the address memory circuit
10
in FIG.
9
.
FIG. 10
shows an example of the conventional address memory circuit formed by using a shift register. When one address is composed of n bits, it is stored in the shift register in the drawing. Since a plurality of addresses are generally assigned to a receiving device, a plurality of register each shown in the drawing are actually provided. In this case, an input
30
is selected by a switching circuit, and address data is written synchronously with a clock
20
. The output is also selected by the switching circuit and inputted into the address comparing circuit. When n is a small value, outputs
331
to
30
+n in the drawing are simultaneously compared with each other, and comparison is sequentially made by switching for every address register. On the other hand, when n is a large value, a terminal corresponding to
31
in the drawing is first selected for all address registers, and the output is inputted into the address comparing circuit. Next, terminals are sequentially switched to
32
,
33
, and the outputs till
30
+n are inputted into the address comparing circuit. The sequence of selection may be opposite to this.
FIG. 11
shows an example of the conventional address memory circuit formed by using latches. In the drawing, a latch is written and read through an 8-bit bus line. In the drawing, the number of bits of the address is 18, and an enable bit of the address is added thereto. The output of the address memory circuit is inputted, as Q(0:18), into the address comparing circuit.
As described above, since a plurality of addresses are normally used, a plurality of circuits each shown in the drawing are used and switched by a selector to input an address into the address comparing circuit. The sequence of switching is executed for each address as described before or executed for each of the same bit for a plurality of addresses.
As a protocol decoding IC for communication used for a pager or the like, one shown in
FIG. 13
is conventionally used. In the drawing, a signal inputted through an input terminal C is processed by a decoding means
50
, and is outputted as data. This decoding process is referred to as protocol decoding. In this prior art, the decoding means
50
includes a synchronization correcting circuit
5
, and an error correcting circuit
6
, a signal detecting circuit
7
, and a synchronization code detecting circuit
8
which receive the output of the circuit
5
. The output of the decoding means
50
is inputted into an informing means
Fujii Isamu
Hishiki Yuji
Idomukai Shinichi
Adams & Wilks
Hunter Daniel
Nguyen Thuan T.
Seiko Instruments Inc.
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