Semiconductor integrated circuit fabrication method

Details Semiconductor integrated circuit fabrication method Semiconductor integrated circuit fabrication method

1989-02-02

1990-08-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 31, 437162, 437968, 357 34, 357 59, H01L 21331

Patent

active

049467980

ABSTRACT:
In a semiconductor integrated circuit fabrication method, isolated regions are in a silicon substrate, which is then covered with polysilicon, a passive base region is then formed, the polysilicon is selectively oxidized, the unoxidized polysilicon is then doped at first and second concentrations, a surface insulating layer is then deposited, the dopant is then diffused from the polysilicon to create further passive and active base regions, contact holes are then opened, the polysilicon above the active base is then doped, and this dopant is then diffused to create an emitter region in the active base. By employing a polysilicon layer with reduced initial thickness, this fabrication method enables precise doping with excellent control over the active base concentration, junction depth, polysilicon sheet resistance, and other parameters. It also enables the base junction depth to be reduced and the eptitaxial layer to be made thinner than before, leading to a high gain-bandwidth product, high switching speed, and generally reduced device dimensions.

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patent: 4495010 (1985-01-01), Kranzer
patent: 4735912 (1988-04-01), Karakatsa
patent: 4778774 (1988-10-01), Blassfeld
patent: 4780427 (1988-10-01), Sakai et al.
patent: 4783422 (1988-11-01), Kawakatsa
Wolf et al., "Silican Processing . . . ", 1986 pp. 186-189.
Sze "Vlsi Tech.", 1983 pp. 106-109.

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