Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2005-05-31
2005-05-31
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S145000, C365S195000
Reexamination Certificate
active
06901026
ABSTRACT:
A semiconductor integrated circuit device includes a memory, /CE transition detector, address transition detector, /WE transition detector and controller. The controller includes a timeout circuit. The timeout circuit generates an internal circuit control signal with preset width to control access to the memory based on detection results of the above transition detectors. The operation of the memory is controlled by the timeout circuit at the read time. The operation of the memory is controlled by the timeout circuit when transition of the end of a /WE signal is detected by the /WE transition detector before a timing specified by the timeout circuit at the write time. Further, the operation of the memory is controlled in response to the transition of the /WE signal when the transition of the end of the /WE signal is detected by the /WE transition detector after passage of the above timing.
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Oikawa Kohei
Shiratake Shinichiro
Takeuchi Yoshiaki
Ho Hoai
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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