Semiconductor integrated circuit devices with protective means a

Details Semiconductor integrated circuit devices with protective means a Semiconductor integrated circuit devices with protective means a

1982-03-03

1985-04-02

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 2313, 357 41, 357 51, 307200B, H01L 2990, H01L 2978, H01L 2702

Patent

active

045090670

ABSTRACT:
An additional N.sup.+ region is provided in a P type substrate adjacent to a protective N.sup.+ resistor region with an insulating layer and metal layer interposed between the N.sup.+ region and the N.sup.+ resistor region. The N.sup.+ resistor region, the oxide layer, the polysilicon layer and N.sup.+ region constitute an MOS transistor, respectively corresponding to a drain region, a gate insulating layer, a gate electrode and a source region of the MOS transistor. When a very high excessive voltage that otherwise would destroy the PN junction between the substrate and the resistor region is applied to the input terminal, the MOS transistor is rendered conductive and the excessive voltage is absorbed.

REFERENCES:
patent: 4394674 (1983-07-01), Sakuma et al.
patent: 4423431 (1983-12-01), Sasaki

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