Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Patent
1997-06-03
1999-03-09
Hardy, David B.
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
257207, 257208, H07L 27118
Patent
active
058804935
ABSTRACT:
In a circuit cell band having circuit cells arranged aligned along a linear array, an on-a-cell line is arranged over a prescribed number of circuit cells, in a region different from a line region in which line band is formed on both sides of the circuit cells, for example, and the on-the-cell line is connected to a feed through in a feed through region provided between adjacent circuit cells. Restrictions on the feed through, size of the circuit cell and the lines are removed as much as possible. The circuit cell has also island-shaped impurity regions for fixing a substrate potential, so that latch up immunity is improved. Transistor forming regions having different conductivity types in a circuit cell are arranged in a sandwiched structure, and the circuit cell can be inverted horizontally and/or vertically while maintaining the transistor arrangement in the circuit cell. Therefore, position of the signal input/output port of the circuit cell can be changed in accordance with the layout of external lines, whereby optimization of the external line layout is facilitated.
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patent: 4989062 (1991-01-01), Takahashi et al.
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patent: 5416431 (1995-05-01), Strauss
"A Smart Design Methodology For Advanced Memories", Arimoto et al., VLSITSA Proceedings Of Technical Papers, May 12-14, 1993, pp. 348-352.
Hardy David B.
Mitsubishi Denki & Kabushiki Kaisha
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