Semiconductor integrated circuit device with test interface...

Details Semiconductor integrated circuit device with test interface... Semiconductor integrated circuit device with test interface...

2001-02-14

2002-09-24

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06456560

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly, to a system LSI (Large Scale Integrated circuit) with a logic and a memory being merged therein. More specifically, the present invention relates to an arrangement of a test interface circuit for testing a memory within the system LSI directly from an outside.
2. Description of the Background Art
In a system LSI such as a logic-merged DRAM in which a logic such as a processor or an ASIC (Application-Specific Integrated Circuit) and a dynamic random access memory (DRAM) of a large storage capacity are integrated on the same semiconductor chip (semiconductor substrate), the logic and the memory such as a DRAM are interconnected by a multi-bit internal data bus of 128 bits to 512 bits so that a data transfer speed that is ten times to hundred times faster than a general-purpose DRAM can be achieved. In addition, the DRAM and the logic are connected by internal interconnection lines which are sufficiently short and which have a small parasitic impedance in comparison with the wiring provided on the board, so that the charging/discharging current of the data bus can be significantly reduced and the signal transfer can be performed at a high speed. Moreover, since the logic and the DRAM are connected by internal interconnection lines, the number of external pin terminals for the logic can be reduced when compared with the case in which a general-purpose DRAM is provided externally to the logic. For these reasons, a DRAM-embedded system LSI substantially contributes to improving the performance of the information equipment for performing processes handling a large amount of data, such as three-dimensional graphic processing, image and audio processing, and the like.
In a system LSI such as the above logic-merged DRAM, the logic alone is coupled to terminals via pads. Consequently, when the functions of a memory such as an embedded DRAM are to be tested, the test must be performed through the logic. In this case, however, the logic will have to perform the control for the test, which imposes a greater load on the logic. Moreover, an instruction for performing a functional test of the memory such as a DRAM must be provided from outside to the logic, which in turn provides a control signal for performing the functional test to the memory such as the DRAM, and the test result must be externally read out through the logic. Thus, the functional test for the memory such as a DRAM would be carried out through the logic so that the test on the operation timing margin and the like of the DRAM cannot be performed with accuracy. In addition, from the viewpoint of program capacity, it is difficult to fully ensure the reliability of the memory such as a DRAM since the number of test patterns generated by the logic would be limited and sufficient testing cannot be performed. Furthermore, the increase in gate scale results in a higher rate of defects in the logic itself, which leads to a lower reliability of the memory test. As a result, there is a need to test the memory such as a DRAM directly from outside via a test apparatus.
FIG. 17
is a schematic representation of the arrangement of a conventional DRAM-embedded system LSI. In
FIG. 17
, a system LSI
900
includes a large-scale logic LG coupled to an external pin terminal group LPGA for performing an instructed processing, an analog core ACR coupled between large-scale logic LG and an external pin terminal group APG for performing a processing related to an analog signal, a DRAM core MCR coupled to large-scale logic LG via internal interconnection lines for storing data required by large-scale logic LG, and a test interface circuit TIC for disconnecting large-scale logic LG from DRAM core MCR and for coupling an external memory tester to DRAM core MCR via a test pin terminal group TPG in a test mode. DRAM core MCR receives a power-supply voltage VCC via a power-supply pin terminal PST.
Analog core ACR includes a phase-locked loop circuit (PLL) for generating an internal clock signal, an analog/digital converter for converting an external analog signal into a digital signal, and a digital/analog converter for converting a digital signal received from large-scale logic LG into an analog signal and outputting the converted signal.
DRAM core MCR is a clock synchronous memory (SDRAM: Synchronous Dynamic Random Access Memory) which takes in data and an operating mode designation signal and outputs data in synchronization with a clock signal.
Large-scale logic LG includes a memory control unit for performing processing, e.g., of image/audio information processing and for controlling access to DRAM core MCR.
As shown in
FIG. 17
, the provision of test interface circuit TIC allows the complete isolation of DRAM core MCR from the logic portion (large-scale logic LG) and the direct access to DRAM core MCR through external test pin terminal group TPG, enabling direct external control and external monitoring of DRAM core MCR. Such a testing technique is referred to as the direct memory access test. By providing this test interface circuit TIC, the conventional memory tester can be utilized, and the tests of substantially the same contents as those for the general-purpose DRAM (SDRAM) can be performed.
FIG. 18
is a diagram representing the arrangement of test interface circuit TIC shown in
FIG. 17 and a
portion related to test interface circuit TIC. In
FIG. 18
, test pin terminal group TPG includes a pin terminal for receiving a test clock signal TCLK
1
, a pin terminal for receiving a test control signal TCMD for designating a test operating mode, a pin terminal for receiving a test address TAD for designating a memory cell to be accessed in DRAM core MCR in a test mode, a pin terminal for receiving write data TDin in the test mode, and a pin terminal for receiving output data TDout from test interface circuit TIC in the test mode. Test write data TDin applied to test interface circuit TIC and test data TDout output from test interface circuit TIC are made to have a bit width of, for instance, 8 bits as in the case of the general-purpose DRAM.
Test interface circuit TIC includes a latch/command decoder
1
for performing such operations as taking in test control signal TCMD, test address TAD, and test write data TDin applied to test pin terminal group TPG in synchronization with test clock signal TCLK
1
, decoding the test control signal into an internal command (operating mode designation signal) to be issued to DRAM core MCR, and expanding test input data TDin of 8 bit width to write data of 256 bits; a mode register
2
for storing information such as column latency of DRAM core MCR; a CA shifter
3
for shifting a read select designation signal received from latch/command decoder
1
according to the column latency information stored in mode register
2
to generate a read data selecting signal RD_S; and a 256 to 8 selection circuit
4
for selecting data of 8 bits from test read data TFIDout of 256 bits read from DRAM core MCR according to read data selecting signal RD_S from CA shifter
3
.
As test peripheral circuits, there are provided a selector
5
for selectively coupling DRAM core MCR to one of the large-scale logic and test interface circuit TIC in response to a test mode designation signal TE, a gate circuit
6
for receiving a clock signal applied from, for example, the large-scale logic in a normal operating mode and a test clock signal TCLK
2
applied in a test mode to apply a clock signal DCLK to DRAM core MCR, and a gate circuit
7
for transmitting read data RD of 256 bits read from DRAM core MCR to test interface circuit TIC in activation of test mode designation signal TE. Read data RD of 256 bits read from DRAM core MCR is also applied to the large-scale logic not through selector
5
in order to apply the read data to the large-scale logic at a high speed in the normal operating mode.
DRAM core MCR takes in applied data and signal in synchronization with a DRAM clock signal DCLK a

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