Semiconductor integrated circuit device with self-aligned superh

Details Semiconductor integrated circuit device with self-aligned superh Semiconductor integrated circuit device with self-aligned superh

1995-05-30

1997-01-07

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 55, 437 51, 148DIG10, H01L 21265

Patent

active

055916562

ABSTRACT:
A superhigh speed vertical transistor having an ultra thin base, a vertical NPN transistor having a reverse direction structure for composing an IIL, and a lateral PNP transistor similarly composing an IIL to be an injector are formed on a P-type silicon substrate 1 by self-aligned and integrated. The emitter leading-out part opening of the superhigh speed vertical NPN transistor and the collector leading-out part opening of the vertical NPN transistor having a reverse direction structure are self-aligned to the base leading-out electrode. In the epitaxial layer, the P-type intrinsic base layer of superhigh speed vertical NPN transistor is formed by impurity diffusion from the emitter leading-out electrode formed of polysilicon film, and the P-type base layer of the vertical NPN transistor having a reverse direction structure is formed by ion implantation. By thus forming the superhigh speed vertical NPN transistor having a reverse direction structure in self-aligned process, the superhigh speed vertical NPN transistor of self-aligned type and IIL device may be integrated on a same chip. Besides, by forming the intrinsic base layer of the vertical NPN transistor having a reverse direction structure deeper in junction than the base layer formed by impurity diffusion from the polysilicon emitter electrode for the superhigh speed NPN transistor of self-aligned type, the low concentration epitaxial layer part beneath the intrinsic base layer for composing the emitter of the vertical NPN transistor having a reverse direction structure may be made smaller, thereby avoiding lowering of the current gain of the vertical NPN transistor having a reverse direction structure and lowering of high speed operation of IIL device accompanying accumulation of minority carrier.

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Kanzaki et al., "A New Super High Speed ECL Compatible I.sup.2 L Technology", Int'l Electron Devices Meeting, pp. 328-331 (Dec. 3-5, 1979).
European Search Report dated Sep. 18, 1995.
T. Nakamura et al., "Self-Aligned Transistor with Sidewall Base Electrode", IEEE Transactions On Electron Devices, vol. ED-29, No. 4, Apr. 1982.

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