Semiconductor integrated circuit device with reduced clock signa

Details Semiconductor integrated circuit device with reduced clock signa Semiconductor integrated circuit device with reduced clock signa

1995-08-21

1997-02-11

Loke, Steven H.

Textiles: manufacturing

257208, 257210, 257211, 257659, 257202, H01L 2710, H01L 23552

Patent

active

056024061

ABSTRACT:
It is an object of the present invention to design in a short period of time a semiconductor integrated circuit device capable of stable operation with high noise margin by reducing effects of noise caused by coupling capacitance between clock signal lines and other signal lines in a semiconductor integrated circuit device with a finer structure. A macro-cell (1a) used in designing with a Computer Aided Design system has a structure in which a clock signal line (6) is interposed and shielded between V.sub.DD power-supply lines (4 and 4a). By using such a basic macro-cell (1a) with the shielded clock signal line (6), coupling capacitance can always be reduced between the clock signal lines and other signal lines formed in interconnection spaces even when using the Computer Aided Design.

REFERENCES:
patent: 4870300 (1989-09-01), Nakaya et al.
IEEE 1989 Custom Integrated Circuits Conference, C. NG, et al., "A Hierarchical Floor-Planning, Placement, and Routing Tool for Sea-Of-Gates Designs", pp. 3.3.1-3.3.4.
L. Wakeman, "Vorgange auf Leitungen und Ihr Einfluss auf HCMOS-Schaltkreise", Der Elektroniker, No. 3, 1986, pp. 57-63.

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