Static information storage and retrieval – Interconnection arrangements
Patent
1997-01-27
1997-09-23
Clawson, Jr., Joseph E.
Static information storage and retrieval
Interconnection arrangements
365 72, 257776, G11C 506
Patent
active
056711735
ABSTRACT:
The present invention discloses a semiconductor integrated circuit device. This semiconductor integrated circuit has metal wiring layers of four levels including peripheral circuits of a memory module which are formed by word and bit lines in a lattice arrangement. The word lines are provided in the first-level metal wiring layer and the bit lines are provided in the second-level metal wiring layer. Provided in the third-level metal wiring layer is a first over-memory wire without direct access to any memory cell. A second over-memory wire without direct access to any memory cell is provided in the fourth-level metal wiring layer. The first and second over-memory wires for establishing connections between functional circuit blocks, are arranged in such a way that they extend across the word lines and the bit lines at an angle of 45 degrees.
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Clawson Jr. Joseph E.
Matsushita Electric - Industrial Co., Ltd.
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