Semiconductor integrated circuit device with noise filter

Details Semiconductor integrated circuit device with noise filter Semiconductor integrated circuit device with noise filter

2002-08-23

2003-12-02

Phung, Anh (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S230030

Reexamination Certificate

active

06657879

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, and more specifically, to a semiconductor integrated circuit device with a noise filter for removing noise of an input signal.
2. Description of the Background Art
In order to meet the demand for a semiconductor memory of large capacity and high speed, a semiconductor integrated circuit device with a plurality of memory units and a memory controller for controlling accesses to the memory unit, referred to as a memory module, has been developed.
FIG. 8
is a schematic block diagram showing a configuration of a memory module according to the conventional technique.
Referring to
FIG. 8
, a memory module
100
according to the conventional technique includes a plurality of memory units
102
, a memory controller
104
, and a plurality of connector terminals
106
.
Each of the memory units
102
is, for example, configured with a Dynamic Random Access Memory (DRAM), and is capable of executing reading and writing data independent of each other.
The memory controller
104
controls the operation of the plurality of memory units
102
in response to a control signal from the outside of the memory module, for example from a system controller (not shown), to control the overall system in which the memory module is integrated. The memory controller
104
is, for example, configured with a Programmable Logic Device (PLD) and generates a memory control signal MCS to control the operation of the plurality of memory units
102
in response to a control signal input to an input pin P
0
. Each of the memory units
102
operates in response to the memory control signal MCS.
Each of the connector terminals
106
is capable of sending and receiving signals to and from the outside of the memory module.
In
FIG. 8
, one connector terminal
106
a
of the plurality of connector terminals is used to show an input path of a control signal input from the system controller to a memory controller
104
.
A noise filter
108
is placed between the connector terminal
106
a
to which a control signal is input and an input pin P
0
of the memory controller
104
. The noise filter
108
removes high frequency components from the signal input to the connector terminal
106
a
by means of a low pass filter composed of a resistance element
109
and a capacitor
110
, and sends the signal to the input pin P
0
. Thus, noise superposed onto the control signal due to an impedance mismatch of an interconnection or the like can be suppressed.
FIG. 9
is a circuit diagram showing a configuration of an input first stage circuit in a memory controller in accordance with the conventional technique.
Referring to
FIG. 9
, the input first stage circuit
105
of the conventional memory controller
104
has inverters IV
1
and IV
2
for receiving a control signal that has been passed the noise filter
108
and sent to the input pin P
0
. Thus, a signal that is of the same phase with the control signal that has been removed of the high frequency noise by the noise filter
108
can be sent into the memory controller.
In the memory module according to the conventional technique such as shown in
FIG. 8
, however, it is required to design the noise filter
108
every time to conform to the system in which the memory module is incorporated. Particularly, it is highly required to design the capacitance of the capacitor
110
in the noise filter
108
at the optimal value since it may lead to transmission delay, i.e. to an increase of the access time to the memory module.
Accordingly, it has been necessary to tune the constant of elements of the noise filter that matches to the system, while evaluating on an actual device with the memory module actually incorporated into the system. In other words, there has been a problem that the noise filter can not be designed for general purpose and thus aggravating the burden for designing the same.
SUMMARY OF THE INVENTION
The objective of the present invention is to design a noise filter for input signals easily in a semiconductor integrated circuit device represented by a memory module.
A semiconductor integrated circuit device according to the present invention includes a plurality of connector terminals for externally sending and receiving signals, a plurality of internal circuits, and a control circuit for controlling the operation of the plurality of operations based on the prescribed logic operation responding to the control signal having been input to one of the plurality of connector terminals. The control signal includes a first pin terminal for receiving an input of a control signal, a second pin terminal for receiving an input of an electric signal, a filter circuit for attenuating components superposed onto the signal input to the first pin terminal in a prescribed frequency range that varies depending on the electric signal input to the second pin terminal, and a logic operation circuit for performing the prescribed logic operation in response to the control signal passing the filter circuit.
Such a semiconductor integrated circuit device is capable of adjusting the frequency characteristic of the filter circuit that act as a noise filter, in response to the electric signal input to the pin terminal of the control unit. Accordingly, noise can effectively be removed without modifying the design of the filter circuit so as to conform to the system in which the semiconductor integrated circuit device is incorporated.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 6208548 (2001-03-01), Kawagoe
patent: 6452826 (2002-09-01), Kim et al.
patent: 6480409 (2002-11-01), Park et al.
patent: 5-122006 (1993-05-01), None
patent: 7-58588 (1995-03-01), None
patent: 8-340236 (1996-12-01), None

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