Semiconductor integrated circuit device with MISFETS using two d

Details Semiconductor integrated circuit device with MISFETS using two d Semiconductor integrated circuit device with MISFETS using two d

1987-11-04

1990-07-03

Munson, Gene M.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

357 239, 357 41, 357 42, 357 63, 357 91, H03K 3353, H01L 2978, H01L 2702, H01L 29167

Patent

active

049393863

ABSTRACT:
Disclosed in an N-type MISFET having the LDD structure in which the short-channel effect is reduced by employing arsenic, which has a smaller diffusion coefficient value than that of phosphorus, to form low- and high-impurity concentration regions which constitute in combination source and drain regions of the MISFET.

REFERENCES:
patent: 4356623 (1982-11-01), Hunter
patent: 4404733 (1983-09-01), Sasaki
patent: 4672419 (1987-06-01), McDavid
patent: 4736233 (1988-04-01), McDavid
patent: 4745086 (1988-05-01), Parillo et al.
patent: 4784965 (1988-11-01), Woo et al.
"Full LDD Devices Fabricated by Photoresist Planarization" IBM Tech. Disclosure Bulletin vol. 27, (3/85) pp. 5699-5700.
"Microdevices" Nikkei Electronies, Aug. 22, 1983, Nikkei McGraw-Hill, pp. 82-86.

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