Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2002-01-09
2004-03-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S208000, C257S069000, C257S204000
Reexamination Certificate
active
06710371
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to layout patterns of semiconductor integrated circuit devices. More specifically, it relates to layout patterns of semiconductor integrated circuit devices constituted such that layouts of functional circuit groups spread in one direction on a chip.
2. Description of Related Art
Conventionally, as one of the manners to meet the needs of higher integration of die size in semiconductor integrated circuit devices, there has been used a layout manner such that arrange functional circuits in a direction along with flow of signals to make up functional circuit groups wherein the functional circuits are constituted by CMOS units composed of pairs of PMOS transistors and NMOS transistors, and a plurality of logic circuits are included therein. This layout manner is applied to semiconductor memory devices such as dynamic random access memory excluding gate array type and standard cell type, i.e., so-called customized products.
It should be noted that CMOS unit or unit mentioned hereinafter indicates some types of unit structured with a pair of one or more PMOS transistors and one or more NMOS transistors, wherein the number of PMOS transistor(s) and that of NMOS transistor(s) are appropriately combined case by case. That is, circuit units that constitute fundamental functions of logic gate, transfer gate, and the like correspond to CMOS unit or unit. Furthermore, a single PMOS transistor or a single NMOS transistor can be classified into a type of unit herein as long as it is used as a capacitance element or a resistance element that has fundamental circuit function. Some elements not constituted by a PMOS transistor or an NMOS transistor are not always classified into unit. For example, a wiring layer switch for trimming, described later, cannot be a unit. This wiring layer switch determines connection between elements to constitute a fundamental circuit element. A group of elements connected by the wiring layer switch constitutes a fundamental circuit element and this corresponds to a unit. Accordingly, each element of the group is not defined as a unit. Furthermore, a capacitance element, a resistance element or the like are not classified into unit, either. This is because elements themselves can be buried in a wiring region and do not influence on element characteristics, layout efficiency or the like.
Layout manners of the gate array type and standard cell type are such that wirings are applied crosswise along a predetermined wiring grid pitch in a certain plot spreading two-dimensionally on a chip. Such layout aims to shorten connection processing time. On the other hand, the layout manner to arrange functional circuit groups in a direction along flow of signals aims to layout circuits with as high integration as possible on a restricted region making full use of restricted wiring layers.
FIG. 18
shows an example of chip layout for a semiconductor integrated circuit device to which three-metal layered processing is applied. A chip for the semiconductor integrated circuit device includes two memory cell regions M
1
and M
2
spreading in Y-direction. Between the memory cell regions M
1
and M
2
, there are arranged functional circuit groups FNBL
1
, FNBL
2
through FNBLn spreading in X-direction taking layout width BW
1
, BW
2
through BWn, respectively in Y-direction. There are wired a power voltage wiring VCC extending from a power voltage pad VCP and a reference voltage wiring VSS from a reference voltage pad VSP across the functional circuit groups FNBL
1
, FNBL
2
through FNBLn to supply power voltage VCC and reference voltage VSS to the functional circuit groups. Both the power voltage wiring VCC and the reference voltage wiring VSS are wired with a third metal layer M
3
L, a top layer. For higher circuit integration, each of the functional circuit groups FNBL
1
, FNBL
2
through FNBLn is laid-out taking each of their layout widths at minimum.
FIG. 19
is an enlarged diagram of a portion
100
(shown in
FIG. 18
) directed to the functional circuit group FNBL
1
. The portion
100
of the functional circuit group FNBL
1
consists of logic circuits CIR
110
, CIR
120
, CIR
130
, and CIR
140
. Each of the logic circuits CIR
110
, CIR
120
, CIR
130
, and CIR
140
constitutes a CMOS unit. For example, in the CIR
110
, PMOS transistors P
1
, P
2
, P
3
and NMOS transistors N
1
, N
2
, N
3
are paired, respectively, to constitute three CMOS units. Connection wirings LV
100
connect P-type and N-type MOS transistors. First metal layer M
1
L, bottom metal wiring layer, is used for the connection wirings LV
100
. As examples of CMOS units, here are shown an inverter gate, a transfer gate, and the like wherein a PMOS transistor and an NMOS transistor are connected one to one. However, types of CMOS unit are not limited to the above. Various logic gates such as NAND gate, NOR gate, MOS capacitor or the like, and fundamental circuit elements also are constituted with CMOS units. Furthermore, on a layer above of the PMOS transistors, there is wired a power voltage wiring VCC
100
for supplying power voltage VCC to the functional circuit group FNBL
1
with second metal layer M
2
L. The power voltage wiring VCC
100
and a power voltage VCC wired with third metal layer M
3
L are connected by VIA contacts CVV at their crossing portion. Similarly, on a layer above of the NMOS transistors, there is wired a reference voltage wiring VSS
100
for supplying reference voltage VSS to the functional circuit group FNBL
1
with second metal layer M
2
L. The reference voltage wiring VSS
100
and a reference voltage VSS wired with third metal layer M
3
L (not shown) are connected by VIA contacts at their crossing portion. Furthermore, between the power voltage wiring VCC
100
and the reference voltage wiring VSS
100
both wired with second metal layer M
2
L, there are wired internal wirings LH
100
in accordance with necessity. In the internal wirings LH
100
, there are wired: input/output wirings for the functional circuit group FNBL
1
; internal wirings LH
100
for connecting between pairs of PMOS-NMOS for CMOS units or between logic circuits CIR
110
through CIR
140
; and the like. A block width BW
1
for the functional circuit group FNBL
1
is determined by the following three factors: (1) a width of the power voltage wiring VCC
100
in response to current capacity required for the functional circuit group FNBL
1
; (2) a width of the reference voltage wiring VSS
100
; and (3) the number of the internal wirings LH
100
determined by circuit structure and layout of the functional circuit group FNBL
1
. Block widths FNBL
2
through FNBLn are determined by the same factors as the above.
In the forgoing, as metal layers, there have been mentioned first metal layer M
1
L, second metal layer M
2
L, and third metal layer M
3
L. In addition to them, there is poly-silicon (referred to as PolySi, hereinafter) layer as gate electrodes of the MOS transistors. That is, it is a four-layered wiring structure. There can be conceived of various processes to realize this four-layered wiring structure.
FIG. 20
shows examples of possible processes. With process A, direct connections between adjacent layers are possible. That is, a VIA contact Cvv connects third metal layer M
3
L and second metal layer M
2
L, a VIA contact Cv connects the second metal layer M
2
L and first metal layer M
1
L, and a contact Cp connects the first metal layer M
1
L and PolySi layer. On the contrary, with process B, ohmic contact between PolySi layer and first metal layer M
1
L is impossible. Accordingly, it is required that a contact Cpp should connect the PolySi layer and second metal layer M
2
L. Accordingly, designers must design layouts of functional circuit groups FNBL
1
through FNBLn taking process factors such as the above into consideration.
FIG.
21
and
FIG. 22
show structural differences of internal wirings LH
100
derived from differences of manufacturing processes.
FIG. 21
shows a layout diagram in case the process A is applied thereto wh
Kitahara Terumasa
Yasuda Koichi
Arent Fox Kintner Plotkin & Kahn
Nguyen Thinh T
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