Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means
Reexamination Certificate
2000-06-01
2002-01-15
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular chip input/output means
C257S207000, C257S208000, C257S210000
Reexamination Certificate
active
06339234
ABSTRACT:
This application claims the benefit of Japanese application No. 11-178724, filed Jun. 24, 1999, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
The present invention relates generally to a semiconductor integrated circuit device, and more particularly to the technology associated with the structure and layout of a semiconductor integrated circuit, which is created particularly in consideration of the protection from electrostatic breakdown and the compatibility with automatic layout.
In semiconductor integrated circuit devices, the percentage of automatic designing has been increased for a protection circuit in input/output circuits and internal circuits by locating electrodes, loop wires & input/output circuits, and internal circuits from a peripheral region to a central region in order, and by connecting respective power wires, which extend from the electrodes to the internal circuits, to the loop wires on route (see
FIGS. 5A and 5B
, and Description of Prior Art in JP-A-5-145015). The protection circuit may be formed between a power and a ground lines associated with the input and output circuit (see FIGS.
6
A and
6
B), or formed through input and output lines (prior art examples shown in JP-A-10-74893, and so on). Also, a protection circuit formed in an elongated region is also known for enhancing the protection ability to the electrostatic breakdown (see JP-A-6-224372).
Among semiconductor integrated circuit devices as mentioned, detailed description will be given on an IC chip
1
, the structure of which is illustrated in
FIGS. 5A and 5B
.
FIG. 5A
generally illustrates the layout of the IC chip
1
, and
FIG. 5B
is a schematic diagram illustrating a main portion of the IC chip
1
in perspective view.
FIGS. 6A and 6B
in turn illustrate the structure of a protection circuit in input/output circuits of the IC chip
1
, wherein
FIG. 6A
is a schematic vertical sectional view, and
FIG. 6B
illustrates an equivalent circuit which is assumed in consideration of a discharge to ground terminal or powering terminal. Further,
FIGS. 7A and 7B
illustrate equivalent circuits which are assumed in consideration of a discharge to grounded terminals and so on over the entire circuit, wherein
FIG. 7A
illustrates a circuit diagram in favor of spatial relative positions of components, whereas
FIG. 7B
illustrates a circuit diagram in favor of discharge paths through the components.
The IC chip
1
is generally formed in the shape of a quadrilateral thin plate by dicing a semiconductor substrate such as a silicon wafer having integrated circuits formed on the main surface thereof. The layout of the integrated circuit is designed in such a manner that a large number of electrodes
2
,
3
,
4
for external connections such as bonding pads are located in peripheral regions along the four sides. A majority of the electrodes are assigned to I/O pads
2
for signal input/output, and some of the remaining electrodes are assigned to a Vdd pad
3
for power supply and a GND pad
4
for grounding, which are formed in pair, in order to supply operating power to an internal circuit
8
and an I/O circuit
7
from the outside. Inside the electrodes
2
,
3
,
4
, the integrated circuit includes a Vdd line (loop wire)
5
made of aluminum or the like and formed in a loop-like wiring pattern, and a GND line (another loop wire)
6
which makes a round inside the Vdd line
5
. Further, the I/O circuit (input/output circuit)
7
is disposed between and underlying these loop wires
5
,
6
. In a remaining central portion of the IC chip, the internal circuit
8
is disposed.
In addition, an outer Vdd line
5
a
extends inwardly from the Vdd pad
3
(electrode for power supply) and is connected to the Vdd line
5
(loop wire associated therewith); an intermediate Vdd line
5
b
extends inwardly beyond the GND line
6
; and an inner Vdd line
5
c
further extends or branches from the intermediate Vdd line
5
b
, and is eventually connected to the internal circuit
8
. These Vdd lines
5
a
-
5
c
complete one of paired power wires. The other of the paired power wires is completed by an outer GND line
6
a
which extends inwardly from the GND pad
5
(electrode to the ground) beyond the Vdd line
5
and is connected to the GND line
6
(loop wire associated therewith); an intermediate GND line
6
b
which extends further inwardly from the GND line
6
; and an inner GND line
6
c
which further extends or branches from the intermediate GND line
6
b
, and is eventually connected to the internal circuit
8
.
Among these power wires, the outer Vdd line
5
a
, the intermediate Vdd line
5
b
, the outer GND line
6
a
, and the intermediate GND line
6
b
generally present substantially linear simple patterns. Also, these power wires and loop wires
5
,
6
are thicker than branching lines such as the inner Vdd line
5
c
and the inner GND line
6
c
. It should be noted that while
FIG. 5B
illustrates the power lines
5
a
,
5
b
,
6
a
,
6
b
as if they were bonding wires, this is because the illustration emphasizes the three-dimensional appearance to clearly show how connections are made. Actually, they are often formed of multi-layer wiring patterns.
In the region of the I/O circuit
7
(see FIG.
6
A), a number of wells are generally formed for element separation, and transistors and so on may be fabricated therein for driving a variety of input/output signals. For receiving the driving power for the transistors and for protecting the components from an unwanted reverse bias and so on, connections are made to positive and negative supply voltage lines, a ground line, and so on. At the connected locations, diodes
7
a
are explicitly or parasitically provided by PN junctions or the like. The diodes
7
a
may be connected to the overlying Vdd line
5
or GND line
6
. Then (see FIG.
6
B), the diodes
7
a
or equivalent back-flow blocking means, capacitors
7
b
parasitically formed thereby, and so on cause surge noise introduced into signal input/output lines, the GND line
6
and so on to promptly escape to the Vdd line
5
or the like.
Further, the internal circuit
8
is formed with a number of logical circuits, digital or analog signal processing circuits, and so on, corresponding to a variety of applications, wherein the operating power required thereby is supplied through thin wires branched off from the inner Vdd line
5
c
and the inner GND line
6
c
.
A majority of individual circuits within the IC chip
1
is automatically laid out using a design aid tool such as a computer. Specifically, when data such as the chip size, the number of pads and so on are given as design parameters, the positioning of the I/O pads
2
and so on, the routing of the Vdd line
5
and the GND line
6
are automatically determined. Likewise, for the power lines
5
a
-
5
c
and
6
a
-
6
c
, once data on the positioning of the Vdd pad
3
and the GND pad
4
are given as design parameters, the wiring from the pads
3
,
4
to the internal circuit
8
is automatically determined from the design parameters. Further, the other circuits
7
,
8
and branching and routing of power wires connected thereto are also automatically laid out based on other design parameters corresponding to particular applications.
SUMMARY OF THE INVENTION
With a semiconductor integrated circuit device having a layout as described above (see FIGS.
5
A and
5
B), when consideration is made to an electrostatic discharge to a ground terminal connected to the ground electrode
4
and a power terminal connected to the power electrode
3
, the input/output circuit
7
is located closer to the power supply electrodes
3
,
4
than the internal circuit
8
from a spatial point of view (see FIG.
7
A), whereas the internal circuit
8
is located closer to the power supply electrodes
3
,
4
than the input/output circuit
7
from a viewpoint of electric or electronic circuit (see FIG.
7
B), when viewed in the equivalent circuits. For this reason, parasitic resistances
5
d
,
6
d
formed of resistance components, inductance an
Morgan & Lewis & Bockius, LLP
Ngo Ngan V.
Rohm & Co., Ltd.
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