Semiconductor integrated circuit device with embedded...

Details Semiconductor integrated circuit device with embedded... Semiconductor integrated circuit device with embedded...

2003-02-20

2004-07-27

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060

Reexamination Certificate

active

06768699

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device with embedded semiconductor memory device of a large storage capacity. More particularly, the present invention relates to a configuration of a row-related control circuit controlling a row select operation in a clock synchronous DRAM (dynamic random access memory) transferring data in synchronization with a clock signal.
2. Description of the Background Art
FIG. 24
is a diagram schematically showing an overall configuration of a conventional semiconductor memory device. In
FIG. 24
, the semiconductor memory device includes: a plurality of sub-memory arrays SMA
0
to SMA
3
; row decoders RD
0
to RD
3
provided corresponding to respective sub-memory arrays SMA
0
to SMA
3
and each selecting a row of a corresponding sub-memory array; a column decoder CDA provided corresponding to sub-memory arrays SMW
0
and SMA
2
to generate a column select signal selecting a column of sub-memory arrays SMA
0
and SMA
2
; a column decoder CDB provided corresponding to sub-memory arrays SMA
1
and SMA
3
to generate a column select signal selecting a column of sub-memory arrays SMA
1
and SMA
3
; a data path DPA for supplying/receiving data to/from a memory cell on a column selected by column decoder CDA; and a data path DPB for supplying/receiving data to/from a memory cell on a column selected by column decoder CDB. Data paths DPA and DPB each include data input circuitry (an input buffer and a write buffer) and data output circuitry (an output buffer and a preamplifier).
Sub-memory arrays SMA
0
and SMA
1
constitute a bank BA#
1
and sub-memory arrays SMA
2
and SMA
3
constitute a bank BA#
0
. A main control circuit MCK is provided in common to banks BA#
1
and BA#
0
and receives an address signal ADD and a command CMD instructing a operating mode in synchronization with a clock signal CLK to generate an operation control signal for banks BA#
0
and BA#
1
.
The semiconductor memory device is a clock synchronous semiconductor memory device operating in synchronization with clock signal CLK, a control signal and an address signal are supplied in synchronization with clock signal CLK and data DQ is transferred in synchronization with clock signal CLK.
A sub-control circuit SCK
0
is provided to bank BA#
0
and a sub-control circuit SCK
1
is provided to bank BA#
1
.
A main control circuit MCK generates an operation control signal for a bank designated according to a bank address included in address signal ADD. Sub-control circuits SCK
0
and SCK
1
each generate a control signal for performing a designated operation according to a main operation control signal from main control circuit MCK. Each of sub-control circuits SCK
0
and SCK
1
operates according to an operation control signal from main control circuit MCK independently of the other.
By dividing a memory array into two banks BA#
0
and BA#
1
as shown in
FIG. 24
, banks BA#
0
and BA#
1
can be activated/deactivated independently of each other by sub-control circuits SCK
0
and SCK
1
. Activation of a bank indicates a state that a memory cell row is placed in a selected state in the bank. By making a data access in an interleaved manner to banks BK#
0
and BK#
1
, a high speed access can be achieved without a penalty on page switching.
FIG. 25
shows a configuration of sub-memory arrays SMA
0
to SMA
3
shown in
FIG. 24
schematically. Sub-memory arrays SMA
0
to SMA
3
are of the same configuration, and therefore, in
FIG. 25
, there is representatively shown one sub-memory array SMA.
In
FIG. 25
, sub-memory array SMA includes: a plurality of memory blocks MB
0
to MB
7
; sense amplifier bands SAB
1
to SAB
7
each placed between adjacent two memory blocks of memory blocks MB
0
to MB
7
and sense amplifier bands SAB
0
and SAB
8
placed outside the respective memory blocks MB
0
and MB
7
.
Memory cells are arranged in rows and columns in each of memory blocks MB
0
to MB
7
. Sense amplifying circuits are provided corresponding to memory cell columns of memory blocks MB
0
to MB
7
in sense amplifier bands SAB
0
to SAB
8
. Sense amplifier bands SAB
0
to SAB
8
are arranged in a so-called “alternate arrangement type shared sense amplifier configuration”, in which sense amplifying circuits are arranged alternately on both sides of columns in a corresponding memory block and each sense amplifying circuit is shared between adjacent blocks.
In a sub-memory array SMA, a row select operation is performed in units of blocks. A memory block is designated by a block select signal generated according to a block address signal included in address signal ADD, and row selection is performed in the designated memory block.
One or two memory blocks are designated at a time. In a case where two memory blocks are simultaneously designated, one memory block is selected among 4 memory blocks in the upper side and one of 4 memory blocks in the lower side is selected. Memory blocks sharing a sense amplifier band are not selected simultaneously.
As sub-memory array SMA is divided into a plurality of memory blocks MB
0
to MB
7
, sub-control circuits SCK
0
and SCK
1
each are divided into local control circuits corresponding to respective memory blocks MB
0
to MB
7
.
In sub-memory array SMA, as shown in
FIG. 25
, partial activation operation (activation in a block basis) is performed with non-selected memory blocks maintained in a precharge state, reducing a current consumption.
Sub-memory arrays SMA shown in
FIG. 25
are arranged in each of banks BA#
0
and BA#
1
. Therefore, at a boundary between banks BA#
0
and BA#
1
, sense amplifier band SAB
8
of bank BA#
1
and sense amplifier band SAB
0
of bank BA#
0
abut on each other. Banks BA#
0
and BA#
1
share no sense amplifier band and the sense amplifier bands of these banks BA#
0
and BA#
1
can be activated and deactivated independently of each other.
FIG. 26
is a diagram schematically showing sub-control circuits SCK
0
and SCK
1
shown in
FIG. 25
schematically. Sub-memory array SMA
2
included in bank BA#
0
includes memory blocks MB
00
to MB
07
. Sub-memory array SMA
0
included in bank BA#
1
includes memory blocks MB
10
to MB
17
. Sense amplifier bands are arranged on both sides of each of memory blocks MB
00
to MB
07
and on both sides of each of memory blocks MB
10
to MB
17
. In
FIG. 26
, there are shown sense amplifier bands each with a rectangular region.
Sub-control circuit SCK
0
includes local control circuits LCK
00
to LCK
07
provided corresponding to respective memory blocks MB
00
to MB
07
and sub-control circuit SCK
1
includes local control circuits LCK
10
to LCK
17
provided corresponding to respective memory blocks MB
10
to MB
17
.
Main control circuit MCK generates a row-related control signal group BRC and a predecode block address PBA for each bank according to a command CMD and address signal ADD externally applied and further generates an internal clock CLK in synchronization with an external clock signal ECLK. Internal clock CLK from main control circuit MCK is applied commonly to local control circuits LCK
00
to LCK
07
and LCK
10
to LCK
17
.
Row-related control signal group BRC specific to each bank includes a row-related control signal BR
0
for bank BA#
0
and a row-related control signal BR
1
for bank BA#
1
. Row-related control signal BR
0
is applied commonly to local control circuits LCK
00
to LCK
07
and row-related control signal BR
1
is applied commonly to local control circuits LCK
10
to LCK
17
.
Predecode block address signal PBA is generated by predecoding a block address included in external address ADD. Since banks BA#
0
and BA#
1
each include 8 memory blocks, predecode block address PBA of 6 bits is generated. Predecode address signal of 2 bits designates the upper half or lower half of memory blocks of each of banks B

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