Semiconductor integrated circuit device with clock...

Details Semiconductor integrated circuit device with clock... Semiconductor integrated circuit device with clock...

2002-09-24

2004-05-18

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S295000, C327S564000

Reexamination Certificate

active

06737903

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices and particularly to a semiconductor integrated circuit device having a plurality of internal circuits that operate in synchronization with a clock signal.
2. Description of the Background Art
For semiconductor integrated circuit devices typified by LSI (large-scale integration), a technique is commonly employed by which the operation timing of internal circuits of a semiconductor integrated circuit device is controlled according to a reference clock signal to allow the internal circuits to operate synchronously.
The semiconductor integrated circuit device having its configuration in which the clock signal is distributed to a large number of internal circuits of the device suffers from a problem of a relative phase shift of the clock signal, which is also called clock skew, due to different paths through which the clock signal is transmitted for example. A configuration generally employed for the purpose of reducing the clock skew distributes the clock signal by one of the so-called clock mesh method and clock tree method.
FIG. 19
schematically shows conventional distribution of a clock signal by the clock mesh method.
Referring to
FIG. 19
, in accordance with the clock mesh method, a mesh distribution network
500
in the form of a grid is provided over the entire area of the semiconductor integrated circuit device. A clock signal CLK is transmitted by a clock driver
520
to mesh distribution network
500
.
An internal circuit
530
is constituted of a flip-flop or data latch that inputs/outputs data in response to clock signal CLK for example. Each internal circuit
530
receives clock signal CLK from a line drawn from the nearest node on mesh distribution network
500
. The clock mesh method is advantageous in that the clock skew between internal circuits
530
is small since all internal circuits
530
are connected with each other with the minimum distance therebetween through mesh distribution network
500
.
However, this mesh-like distribution network has a problem that the total length of lines for transmitting the clock signal is long, which results in a greater amount of charging and discharging current of mesh distribution network
500
and accordingly results in increase in the power consumption.
FIG. 20
schematically shows conventional distribution of a clock signal according to the clock tree method.
Referring to
FIG. 20
, in accordance with the clock tree method, all internal circuits
530
are connected via a distribution node
560
through a tree distribution network
550
in the form of a symmetrical and hierarchical binary tree. In this configuration, propagation delays of clock signal CLK transmitted from an input node Ni to respective internal circuits
530
are theoretically equal to each other. Then, the clock skew at each internal circuit
530
is theoretically zero. Moreover, a clock driver may be provided at distribution node
560
as required for waveform shaping of clock signal CLK.
In particular, the clock driver may additionally have an AND logic function to stop clock signal CLK from being supplied to any inactivated internal circuit. Power consumption of the semiconductor integrated circuit device is thus reduced. This configuration is also called gated clock configuration that is commonly employed by a processor adapted for low power consumption.
The clock tree method, however, actually has difficulty in shaping tree distribution network
550
into the theoretically symmetrical binary tree. Therefore, the effective clock skew could be larger than that of the clock mesh method in many cases.
On the other hand, the clock mesh method is implemented on the precondition that lines constituting mesh distribution network
500
for transmitting the clock signal are connected at low impedance, which makes it difficult to use the gated clock configuration as that of the clock tree method. In other words, the clock mesh method has a problem that power consumption is difficult to cut.
As discussed above, the clock mesh method and the clock tree method which are employed for conventional clock signal distribution respectively have the problem in reduction of power consumption and the problem of clock skew.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a configuration of a semiconductor integrated circuit device having a clock distribution structure for distributing a clock signal with smaller clock skew and lower power consumption.
In summary, according to one aspect of the present invention, a semiconductor integrated circuit device includes a group of clock buses, a plurality of internal circuits, a plurality of clock distribution networks, and a plurality of clock drive control units. The group of clock buses has a hierarchical tree structure provided for transmitting a clock signal. The internal circuits are divided into a plurality of blocks and the internal circuits each receive the clock signal to operate when activated. Activation of the internal circuits is controlled block by block. The clock distribution networks are provided correspondingly to the blocks respectively, each for transmitting the clock signal to the internal circuits of a corresponding one of the blocks. The clock drive control units are provided correspondingly to the blocks respectively, each for supplying the clock signal from the group of clock buses to a corresponding one of the clock distribution networks. Each of the clock drive control units stops supply of the clock signal when internal circuits of the corresponding block are inactivated.
According to another aspect of the present invention, a thin-film magnetic memory device includes a plurality of first internal circuits, a plurality of second internal circuits, a plurality of first clock distribution networks, a plurality of second clock distribution networks, and a connection switch. The first internal circuits are divided into a plurality of first blocks, and the first internal circuits are each activated with receiving a first clock signal to operate. The second internal circuits are divided into a plurality of second blocks, and the second internal circuits each receive a second clock signal to operate when activated. The second clock signal has a frequency N times (N: integer of at least 2) as high as that of the first clock signal and is in phase with the first clock signal. Activation of the first and second internal circuits is controlled block by block. The first clock distribution networks are provided correspondingly to the first blocks respectively, for transmitting the first clock signal to the first internal circuits of corresponding first blocks respectively. The second clock distribution networks are provided correspondingly to the second blocks respectively, for transmitting the second clock signal to the second internal circuits of corresponding second blocks respectively. The connection switch is provided between one of the first clock distribution networks and one of the second clock distribution networks. The connection switch connects that one of the first clock distribution networks and that one of the second clock distribution networks at least when the first internal circuits corresponding to that one of first clock distribution networks and the second internal circuits corresponding to that one of second clock distribution networks are all activated in a period in which respective levels of the first and second clock signals coincide with each other.
Thus, the present invention is chiefly advantageous in that a clock signal is supplied through a hierarchical tree structure to each of clock distribution networks provided respectively for blocks each formed of internal circuits that are commonly controlled for activation. The present invention accordingly enjoys both of respective advantages of the clock tree method and the clock mesh method to distribute the clock signal with low power consumption and small clock skew.
Moreover, a conne

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