Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Patent
1982-11-22
1985-07-02
Salce, Patrick R.
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
361 91, 361111, 357 23, H02H 320
Patent
active
045272131
ABSTRACT:
A semiconductor integrated circuit device has circuits for protecting an input section against an external surge. The device comprises an input terminal, a first resistor connected at one end to the input terminal and a first protective circuit connected between the other end of the first resistor and a reference voltage source for accelerating the discharge of an input surge. The first protective circuit includes a first MOS transistor and a resistor element connected in series to the source-drain path of the first MOS transistor. The integrated circuit further comprises a second resistor connected at one end to the other end of the first resistor, a second protective circuit connected between the other end of the second resistor and the reference voltage source for lowering the potential at the node of the other end of the first resistor and one end of the second resistor, whenever the potential is abnormally high due to the input surge, and a second MOS transistor included in the input section. The gate of the second MOS transistor is connected to the other end of the second resistor for receiving an input signal from the input terminal through the first and second resistors.
REFERENCES:
patent: 3403270 (1968-09-01), Pace et al.
patent: 3819952 (1974-06-01), Enomoto et al.
European Patent Application, published 7-7-82, Inventor--Shigenobu; Pub. No. 55,552.
Japanese Patent Disclosure (KOKAI) No. 54-116887, T. Tsujiide; Sep. 11, 1979.
Japanese Patent Disclosure (KOKAI) No. 53-18979, T. Wada; Feb. 21, 1978.
Salce Patrick R.
Tokyo Shibaura Denki Kabushiki Kaisha
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