Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Utility Patent
1999-03-03
2001-01-02
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S147000
Utility Patent
active
06169435
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device with a built-in timing regulator for output signals.
DESCRIPTION OF THE RELATED ART
A microprocessor is an essential component of a data processing system, and communicates with other system components in synchronism with a system clock. The system clock is getting faster and faster. A microprocessor is synchronous with the system clock at 100 MHz to 300 MKHz. In this instance, the pulse period is only 3 nanoseconds to 10 nanoseconds. The system components are expected to respond to the high-speed system clock.
Logic gates are important circuit components of the system components, and electric signals are propagated through the logic gates. However, the signal propagation speed is not constant between the products, because the manufacturer can not strictly adjust the dimensions of the component transistor and the transistor characteristics such as a current driving capability to respective target value. Moreover, the amount of load to be driven, the environment temperature and a power voltage are not constant. If the difference of signal propagation speed to an output circuit is serious, another system component fails to communicate with the system component. The difference in signal propagation speed may result in a binary value different from the logic operation.
The high-speed system clock merely offers a narrow timing to the system components, and the manufacturer is forced to design the system components to place a multi-bit digital output signal at the output pins within the narrow timing. In other words, the manufacturer designs the system component to satisfy the minimum delay time and the maximum delay time with respect to the system clock. If a system component places the multi-bit digital output signal at the output pins earlier than the narrow timing, another system component fetches the next output signal. On the other hand, if a system component delays the output signal, another system component twice fetches the previous output signal.
As the circuit components of the system are scaled down, the design rules become more sever. If a process parameter fluctuates during the fabrication of the system component on a semiconductor wafer, the circuit components are seriously affected by the process parameter, and the electric properties are liable to be deviated from the target properties.
In order to guarantee the products, the manufacturer checks the product to see whether or not the signal delay falls within the range between the minimum delay time and the maximum delay time before delivery to customers. If a product does not satisfy the design specification, the manufacturer rejects the product as defective. Such a defective product increases the production cost, and is undesirable for the manufacturer. However, the design specification for the output characteristics is getting sever more and more due to the high-speed system clock. The manufacturer feels that the design specification for the output characteristics are not easy to realize.
In fact, the manufacturer thinks that the output characteristics to be required are hardly achieved through improvements of the process. If a fabrication process unavoidably introduces a dispersion of the order of 10 nanoseconds into the output characteristics of a semiconductor integrated circuit device. This dispersion is ignoreable when the system clock is under 10 MHz, because the system clock offers 100 nanoseconds to the semiconductor device. However, if the system clock is increased to 100 MHz, the dispersion is as much as the pulse period of the system clock, i.e., 10 nanoseconds, and the manufacturer can not use the fabrication process for the semiconductor integrated circuit device.
Japanese Patent Publication of Unexamined Application No. 9-181580 proposes to control the delay time by using a variable delay circuit. The variable delay circuit includes a series of delay units, and the delay units are respectively accompanied with AND gates. A control signal is selectively supplied to the AND gates, and causes the selected AND gates to transfer an electric signal to the next delay unit.
The prior art variable delay circuit is regulated to a target delay time before installation on a circuit board for an electronic system. First, an operator connects a tester (not shown) to the output nodes of the delay units, and measures a delay time at each output node. The operator selects one of the output nodes appropriate to the delay time to be required, and the delay units after the selected one are deactivated in order not to propagate the signal.
Even if the transistor characteristics fluctuate due to the fluctuation of process parameter, the fluctuation merely forces the manufacturer to change the appropriate output node from one delay unit to another, and the manufacturer can adjust the prior art delay circuit to the target delay time at all times. However, a problem is encountered in the prior art semiconductor integrated circuit disclosed in the Japanese Patent Publication of Unexamined Application in the production cost.
The tester is expected to exactly measure the delay time. As described hereinbefore, the system clock defines an extremely short pulse period. For this reason, the regulating work requires a highly accurate tester. Such a highly accurate tester is very expensive. Moreover, only a particular kind of tester is available for the prior art delay circuit. Other kinds of tester can not connect the probes to the prior art delay circuit. The manufacturer needs to prepare the particular kind of tester. The expensive tester pushes up the production cost.
Another factor of the high production cost is complexity of the regulation work. The regulation work consumes a large amount of time and labor, and increases the production cost.
Yet another factor of the high production cost is a low production yield due to the severe regulation work. The manufacturer measures the delay time before the installation on the circuit board in order to regulate the delay time to the target value. However, the regulation work is usually carried out in a testing environment different from the actual environment on the circuit board. The different environment such as the temperature affects the transistor characteristics. If the difference between the testing environment and the actual environment is a little, the prior art delay circuit introduces an actual delay time approximately equal to the delay time in the regulation work. However, if the difference is not ignoreable, the prior art delay circuit is causative of malfunction of the electronic system. This means that a margin is required. For this reason, the manufacturer uses a severe specification for the prior art delay circuit. The severer the specification, the lower the production yield. The low production yield results in the high production cost.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a semiconductor integrated circuit device, a delay circuit of which is regulated to a target delay time without an expensive tester in an environment identical with an actual environment on a circuit board for an electric system.
To accomplish the object, the present invention proposes to internally generate an output timing delayed from a system clock by a predetermined delay time.
In accordance with one aspect of the present invention, there is provided a semiconductor integrated circuit device comprising a timing regulator for offering an output timing to output signals, and the timing regulator includes a delayed signal generator supplied with a reference clock signal and producing a delayed clock signal delayed from the reference clock signal by a predetermined time and an output timing generator connected to the delayed signal generator and compensating a time lag between the delayed clock signal and the output signals for outputting the output signals at the output timing.
Fujii Takaharu
Sakai Toshichika
Yashiba Yasuo
Foley & Lardner
NEC Corporation
Nuton My-Trang
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