Electrical transmission or interconnection systems – Miscellaneous systems – For particular load device
Reexamination Certificate
2000-09-06
2002-11-26
Jackson, Stephen W. (Department: 2836)
Electrical transmission or interconnection systems
Miscellaneous systems
For particular load device
C307S149000, C307S038000
Reexamination Certificate
active
06486572
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having an internal circuit and an output circuit that operate on the same source of electric power.
2. Description of the Prior Art
FIG. 8
shows an example of the circuit configuration of a conventional semiconductor integrated circuit device. As shown in this figure, in this device, both an internal circuit
10
and an output circuit
20
operate on the same supplied voltage V
DD
fed from a common electric power source. The output circuit
20
is built as a CMOS inverter circuit composed of a P-channel MOSFET (metal-oxide semiconductor field-effect transistor)
21
and an N-channel MOSFET
22
(hereafter a MOSFET is referred to simply as a “transistor”). The gates of these P-channel and N-channel transistors
21
and
22
are connected together, and their node is connected to the input terminal IN of the output circuit
20
. The source of the P-channel transistor
21
is connected to a terminal D, which is in turn connected to the supplied voltage V
DD
. The source of the N-channel transistor
22
is connected to a terminal G, which is in turn connected to ground GND. The drains of the P-channel and N-channel transistors
21
and
22
are connected together, and their node is connected to the output terminal OUT of the output circuit
20
According to this circuit configuration, when the potential at the input terminal IN turns to a low level, the P-channel transistor
21
is turned on, and the N-channel transistor
22
is turned off, with the result that the potential at the output terminal OUT turns to a high level (equal to the supplied voltage V
DD
). By contrast, when the potential at the input terminal IN turns to a high level, the P-channel transistor
21
is turned off, and the N-channel transistor
22
is turned on, with the result that the potential at the output terminal OUT turns to a low level (equal to the ground level).
Now, consider a case where, as shown in
FIG. 8
, a capacitive load
50
is connected to the output terminal OUT of the conventional semiconductor integrated circuit device described above. When the potential at the input terminal IN of the output circuit
20
turns from a high level to a low level, an electric current flows from the supplied voltage V
DD
through the P-channel transistor
21
so as to charge the load capacitance C
K
. By contrast, when the potential at the input terminal IN of the output circuit
20
turns from a low level to a high level, an electric current flows through the N-channel transistor
22
to ground GND so as to discharge the load capacitance C
K
.
Moreover, it is inevitable that, as shown in
FIG. 8
, small parasitic resistances R
D
and R
G
exist across the power lines, i.e. on the one hand along the path from the supplied voltage V
DD
to the branch node A between the internal circuit
10
and the output circuit
20
, and on the other hand along the path from the confluence node B between the internal circuit
10
and the output circuit
20
to ground.
From the descriptions given above, it will be understood that, as the potential at the input terminal IN of the output circuit
20
turns from a high level to a low level, the current flowing through the resistance R
D
increases, and the current flowing through the resistance R
G
decreases; by contrast, as the same potential turns from a low level to a high level, the current flowing through the resistance R
D
decreases, and the current flowing through the resistance R
G
increases. In this way, every time the potential at the input terminal IN of the output circuit
20
changes its level, the currents that flow through the resistances R
D
and R
G
fluctuate, causing variations in the voltage on which the internal circuit
10
operates and thus destabilizing the operation of the internal circuit
10
.
It is to be noted that, the greater the load capacitance connected to the output terminal OUT, for example as a result of a number of capacitive loads being connected in parallel to the output terminal OUT, and the higher the current capacity of the P-channel or N-channel transistor
21
or
22
, the larger the currents that flow to charge and discharge the load capacitance, and therefore the more serious the effect of the problem. The same is true when a number of output circuits change their output level simultaneously.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit device that ensures stable operation of an internal circuit that operates on the same source of electric power as an output circuit.
To achieve the above object, according to the present invention, a semiconductor integrated circuit device is provided with: a supplied power terminal for receiving electric power; an internal circuit that operates on the electric power supplied thereto via the supplied power terminal; an output circuit that operates on the electric power supplied thereto via the supplied power terminal; and a capacitive circuit element that is connected midway along the power supply path laid from the supplied power terminal to the output circuit and that acts to allow the electric current that occurs as the output circuit is turned on and off to be supplied to and from an output terminal via the output circuit.
In this circuit configuration, connecting a capacitive circuit element in the manner described above makes it possible to supply the current for the charging/discharging of the load capacitance also from the capacitive circuit element. This helps reduce the charge/discharge current required to be supplied from the supplied power terminal. As a result, it is possible to keep constant the current that flows from the supplied power terminal to the power supply path, and thereby reduce the effect on the internal circuit of the variations caused in the supplied voltage by the operation of the output circuit.
REFERENCES:
patent: 3792384 (1974-02-01), Hunt
patent: 4598397 (1986-07-01), Wakabayashi et al.
patent: 4783603 (1988-11-01), Goforth
patent: 5315187 (1994-05-01), Cheng
patent: 5444402 (1995-08-01), McMahon et al.
patent: 6191647 (2001-02-01), Tanaka et al.
Arent Fox Kintner Plotkin & Kahn
Deberadinis Robert L.
Jackson Stephen W.
Rohm & Co., Ltd.
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