Static information storage and retrieval – Powering – Data preservation
Reexamination Certificate
2003-01-16
2004-11-30
Tran, M. (Department: 2818)
Static information storage and retrieval
Powering
Data preservation
C365S233100
Reexamination Certificate
active
06826109
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a technique effectively applied to a large scale integrated circuit having, for example, a RAM macro.
By investigation of known techniques after achieving the present invention, the following report has been made on a technique regarding a memory circuit having two operation modes associated with high response and low power consumption as one of features of the present invention. Japanese Patent Application No. 2000-21165 (corresponding to U.S. Pat. No. 6,266,294) and Japanese Patent Application No. 2001-14847 (corresponding to U.S. Pat. No. 6,292,412) disclose a synchronous memory having an active power-down mode in which a DLL circuit for generating a sync clock is set in an operative state and response is increased and a standby power-down mode in which the operation of the DLL circuit is also stopped to realize low power consumption.
SUMMARY OF THE INVENTION
In each of the techniques, a sync clock generating circuit is provided internally and the application range is limited to the circuit. The inventor herein came up with an idea of providing two modes of a mode assigning a priority on response and a mode assigning a priority on low power consumption by providing two or more signals for activating a memory circuit, such as a clock enable signal and a chip select signal and setting a role to each of the signals. From another viewpoint, the two modes can be used for setting two kinds of setup values of write data.
An object of the invention is to provide a semiconductor integrated circuit device on which a RAM macro or the like with improved ease of use is mounted. Another object of the invention is to provide a semiconductor integrated circuit device on which a RAM macro of which operation mode adapted to either response or low power consumption can be selected. Further another object of the invention is to provide a semiconductor integrated circuit device on which a RAM macro capable of selecting an input setup value can be selected is mounted. The above and other objects and novel features of the present invention will become apparent from the description of the specification and accompanying drawings.
The outline of a representative one of inventions disclosed in the specification will be briefly described as follows. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing.
The outline of another representative one of inventions disclosed in the specification will be briefly described as follows. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.
REFERENCES:
patent: 5422858 (1995-06-01), Mizukami et al.
patent: 5566108 (1996-10-01), Kitamura
patent: 6243320 (2001-06-01), Hamamoto et al.
patent: 6266294 (2001-07-01), Yada et al.
patent: 6292412 (2001-09-01), Kato et al.
patent: 8-102188 (1994-09-01), None
patent: 8-329680 (1995-05-01), None
patent: 2000-21165 (1998-06-01), None
patent: 2001-14847 (1999-06-01), None
Higeta Keiichi
Iwahashi Satoshi
Kanetani Kazuo
Nakahara Shigeru
Suzuki Takeshi
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Reed Smith LLP
Tran M.
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