Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Reexamination Certificate
2003-01-31
2004-12-28
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
C257S211000, C257S691000, C257S738000, C257S759000, C257S778000
Reexamination Certificate
active
06835971
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device of the flip chip bonding type having bump electrodes (protruding electrodes) used for on-circuit-board mounting. The invention also relates to a technique useful for the fabrication of a synchronous SRAM (static random access memory) for example.
Semiconductor integrated circuit devices of the flip chip bonding type having a formation of protruding electrodes such as solder bumps are described in Japanese Patent Unexamined Publications Nos.Hei 5(1993)-218042 and Hei 8(1996)-250498 and U.S. Pat. No. 5,547,740, for example. These patent publications show one of the basic schemes of semiconductor integrated circuit devices of the flip chip bonding type. Specifically, re-wiring lines are laid to run from bonding pads of a chip, and bump electrodes which are connected to the re-wiring lines are arrayed on the chip surface so as to be exposed over beyond the chip surface protection film. A resulting expanded spacing of bump electrodes facilitates the on-board mounting of the chip based on the connection of bump electrodes to wiring lines of a circuit board and ultimately enables the use of inexpensive circuit boards having a large line spacing.
Semiconductor integrated circuit devices have their property of withstand voltage degraded and thus have their operation voltage lowered as the trend of microstructuring of MOS transistors advances. On this account, semiconductor integrated circuit devices are often designed to produce from a higher externally supplied power voltage VDD a lower internal power voltage VDDI for the operation voltage to be supplied to their internal circuits. The lower internal power voltage VDDI is produced from the higher supplied power voltage VDD with a limiter circuit (also called voltage step-down circuit) The limiter circuit is arranged to include a driver PMOS (p-channel MOS) transistor and a differential amplifier which compares the produced power voltage VDDI with a reference voltage Vre and activates the driver PMOS transistor in response to the comparison result. The internal power voltage VDDI results from a voltage drop of the supplied power voltage VDD between the source and drain electrodes of the driver PMOS transistor. A variation of internal power voltage VDDI is evaluated in terms of a comparison result with the reference voltage Vre, and the internal power voltage VDDI is stabilized at the prescribed voltage level on a feedback control basis.
A semiconductor integrated circuit device which is designed to step down the externally supplied power voltage and feeds to the internal circuit is described in Japanese Patent Unexamined Publication No.2002-25260 for example.
SUMMARY OF THE INVENTION
There is a constant trend of higher operation frequencies among semiconductor integrated circuit devices including synchronous SRAMs (static random access memory) and synchronous DRAMs (dynamic random access memory) which operate in synchronism with the clock signal. Consequently, their internal circuits consume increased power.
In regard to this matter, the inventors of the present invention have noticed such anxieties that the limiter circuit and its periphery may be subjected to a harmful heat-up due to the concentration of a large current of internal power voltage VDDI to many internal circuit sections, resulting in a characteristic degradation of the semiconductor integrated circuit device, and that the internal power voltage VDDI may fall due to the large current and the wiring resistance between the limiter circuit and the internal circuit sections, resulting also in a characteristic degradation of the device.
It is an object of the present invention to provide a technique for preventing the characteristic degradation of semiconductor integrated circuit devices.
These and other objects and novel features of the present invention will become apparent from the following description and accompanying drawings.
Among the affairs of the present invention disclosed in this specification, representatives are briefed as follows.
In a semiconductor integrated circuit device having a semiconductor substrate, circuit elements which are formed on the substrate to make up an electrical circuit, a wiring layer which is formed on the substrate and connected electrically to the circuit elements, an organic insulation film which covers the electrical circuit, while having an opening, a conductor layer which is formed by lamination on the organic insulation film and connected electrically to the wiring layer through the opening, and a bump electrode which is connected electrically to the wiring layer by the conductor layer, there are included in the electrical circuit by being scattered across the substrate a plurality of limiter circuits for producing an internal power voltage of a prescribed voltage level, with each limiter circuit including a transistor for lowering the voltage level of an external power voltage which is put in from the outside through the bump electrode. The transistor is formed in an area so as to be arranged just underneath the formation area of the bump electrode used in for taking the power voltage.
According to the scattered layout of limiter circuits across the semiconductor substrate, the concentration of current to one limiter circuit can be avoided and the harmful heat-up of the limiter circuits and their periphery can be alleviated. Moreover, based on the layout of the transistor formation area of the limiter circuit just beneath the bump electrode formation area, the length of wiring from the power-feed bump electrode to the transistor can be reduced. The shorter wiring and thus the smaller wiring resistance contributes to the reduction of voltage drop on the wiring, and the fall of internal power voltage can be alleviated. In consequence, the characteristic degradation of the semiconductor integrated circuit device can be prevented.
The limiter circuit includes a voltage sensing circuit which senses the voltage level of the internal power voltage and a comparison circuit which compares the sensed power voltage level with the reference voltage and controls the conductivity of the transistor in response to the comparison result. The transistor is actually a plurality of p-channel MOS transistors connected in parallel, with at least part thereof being laid out so as to be located just beneath the bump electrode.
Preferably, all the limiter circuits share a single reference voltage generation circuit so that the circuit formation area is minimized.
In a semiconductor integrated circuit device having internal power feed lines for distributing the internal power voltage produced by the limiter circuits, a plurality of memory cells which are arrayed, and a plurality of word lines for selecting memory cells, there are included in the internal power feed lines inter-word-line power lines which are made from a wiring layer common to the word lines and laid between adjacent word lines and over-word-line power lines which are made from a wiring layer different from the layer of word lines, laid to intersect the inter-word-line power lines and connected electrically to them. This spread layout of internal power feed lines reduces the wiring resistance, thereby alleviating the power voltage drop.
The conductor layer can include an internal power feed line which is formed to surround the bump electrode formation area. The conductor layer can further includes an address signal line and low-voltage power feed line which distributes the low power voltage. The address signal line is preferably shielded by the low-voltage power line which is laid alongside the address signal line so that the noise induction and crosstalk are alleviated. The conductor layer can further be used for the conduction of clock signal.
REFERENCES:
patent: 5547740 (1996-08-01), Higdon et al.
patent: 6483176 (2002-11-01), Noguchi et al.
patent: 5-218042 (1992-02-01), None
patent: 8-250498 (1995-03-01), None
Hayashi Atsuhiro
Negishi Takemi
Toyoshima Hiroshi
Uehara Takashi
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Reed Smith LLP
Vu Hung
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