Semiconductor integrated circuit device which shortens the...

Details Semiconductor integrated circuit device which shortens the... Semiconductor integrated circuit device which shortens the...

1999-07-29

2001-06-19

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S544000

Reexamination Certificate

active

06249174

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device incorporated in an analog circuit and used for generation of a reference voltage.
2. Description of the Background Art
As the trend toward multimedia information grows stronger, there is an increasing demand for a system for processing analog signals, such as audio and video signals, at high speeds and with high precision. A hybrid analog-digital LSI circuit which contains a MPU (Micro Controller Unit), a DSP (Digital Signal Processor), and D-A and A-D converters on a single semiconductor chip can achieve lower power consumption in addition to higher-speed and higher-precision operation, and is the mainstream of LSI development.
A digital circuit part of the hybrid analog-digital LSI circuit has been increased in the degree of integration with the progression of a MOS circuit micromachining technique, and has achieved the high-speed operation, high performance and low power consumption. However, the D-A and A-D converters of the hybrid analog-digital LSI circuit which are essential for system input and output have not yet achieved so high a degree of integration and so low power consumption as the digital circuit part under the constrains of machining precision and physical characteristics of transistors under present circumstances.
In recent years, products with the hybrid analog-digital LSI circuit incorporated in transportable equipment have been coming along. However, since the LSI circuit for incorporation in transportable equipment is assumed to be battery-operated, the reduction in power consumption of such an LSI circuit is the highest-priority technical object to be accomplished.
An example of high-speed, high-precision and low-power-consumption D-A converters manufactured using the CMOS process includes a current cell matrix type D-A converter.
FIG. 11
is a block diagram showing the general construction of the current cell matrix type D-A converter.
As illustrated in
FIG. 11
, the current cell matrix type D-A converter comprises a cell matrix MX including a plurality of current source cells SL arranged in a matrix form, an X-decoder XD for specifying the row position of the cell matrix MX, a Y-decoder for specifying the column position of the cell matrix MX, and a reference voltage generator circuit RG for providing an operating voltage to the current source cells SL.
The X-decoder XD receives four bits b
3
, b
2
, b
1
and b
0
of input digital code, and the Y-decoder YD receives four bits b
7
, b
6
, b
5
and b
4
of input digital code. The number of current source cells SL to be turned on is established based on a total of eight bits of input digital code.
Each of the current source cells SL has two outputs I
OUT
and I
OUTB
, the output I
OUT
being grounded through a resistor R
L
, the output I
OUTB
being grounded through a resistor R
LB
.
FIG. 12
shows the construction of a current source cell SL. The current source cell SL of
FIG. 12
comprises an input section including an AND gate G
1
having two inverting inputs and an OR gate G
2
having two inputs one of which is connected to the output of the AND gate G
1
; P-channel MOS transistors (referred to hereinafter as PMOS transistors) M
1
, M
2
, M
3
, M
4
; and N-channel MOS transistors (referred to hereinafter as NMOS transistors) M
5
, M
6
.
In the input section, the two inputs of the AND gate G
1
receive an output from the X-decoder XD and an output from the Y-decoder YD respectively, and the inverting input of the OR gate G
2
receives another output from the Y-decoder YD.
Regarding the construction of the current source cell, the sources of the PMOS transistors M
3
and M
4
are connected to a power supply V
DD
, and the drains of the PMOS transistors M
3
and M
4
are connected to the sources of the PMOS transistors M
1
and M
2
, respectively. The drains of the PMOS transistors M
1
and M
2
provide respectively the outputs I
OUTB
and I
OUT
complementary to each other.
The drain of the PMOS transistor M
3
is connected to the drain of the NMOS transistor M
5
, and the drain of the PMOS transistor M
4
is connected to the drain of the NMOS transistor M
6
. The sources of the NMOS transistors M
5
and M
6
are grounded. The gate of the NMOS transistor M
5
is connected to the drain of the NMOS transistor M
6
, and the gate of the NMOS transistor M
6
is connected to the drain of the NMOS transistor M
5
.
A reference voltage V
BIAS
from the reference voltage generator circuit RG is applied to the gates of the PMOS transistors M
1
and M
2
.
The output from the OR gate G
2
is applied to the gate of the PMOS transistor M
3
and is also inverted by an inverter G
3
. The inverter G
3
applies the inverted output to the gate of the PMOS transistor M
4
.
The operation of the current cell matrix type D-A converter is described below. When predetermined input digital code is applied to the X-decoder XD and the Y-decoder YD, current source cells in the cell matrix MX the number of which corresponds to the input digital code turn on to supply currents which in turn are added together to flow into the load resistor R
L
. Thus, the current cell matrix type D-A converter provides an analog output voltage corresponding to the input digital code.
The reason why the outputs I
OUTB
and I
OUT
from each current source cell SL are complementary to each other is to provide a constant amount of heat generated by the entire device independently of the input digital code.
The reference voltage generator circuit RG is a circuit for generating the reference voltage V
BIAS
required to operate the PMOS transistors M
1
and M
2
of each current source cell SL as a constant current source.
In the above described current cell matrix type D-A converter (also referred to simply as a D-A converter hereinafter), the reference voltage generator circuit RG is designed so that the reference voltage V
BIAS
generated by the reference voltage generator circuit RG during standby equals the voltage of the power supply V
DD
for reduction in power consumption during standby (when the system is suspended).
FIG. 13
shows the construction of the reference voltage generator circuit RG. As illustrated in
FIG. 13
, the reference voltage generator circuit RG comprises NMOS transistors M
7
, M
8
, M
9
, PMOS transistors M
10
, M
11
, M
12
, M
13
, an inverter G
4
, and a resistor R
1
.
The drains of the NMOS transistors M
7
and M
8
are connected to each other, and the sources of the NMOS transistors M
7
and M
8
are grounded. The PMOS transistor M
10
has a drain connected through the resistor R
1
to the drains of the NMOS transistors M
7
and M
8
, and a source connected to the power supply V
DD
. The PMOS transistor M
11
has a gate grounded, a source connected to the power supply V
DD
, and a drain connected to the source of the PMOS transistor M
12
. The PMOS transistor M
12
has a drain connected to the drain of the NMOS transistor M
9
. The NMOS transistor M
9
has a source grounded, and a gate connected to the gate of the NMOS transistor M
8
. The gate of the NMOS transistor M
8
is connected to the drains of the NMOS transistor M
7
and M
8
.
The PMOS transistor M
13
has a source connected to the power supply V
DD
, and a drain connected to the gate of the PMOS transistor M
12
. The gate of the PMOS transistor M
12
is connected to the draw thereof. The drain of the PMOS transistor M
13
and the gate of the PMOS transistor M
12
are connected to an output end VT of the reference voltage V
BIAS
.
A stop signal STOP which is one of the control signals provided from the exterior of the D-A converter is input to the gate of the PMOS transistor M
10
and the gate of the NMOS transistor M
7
. An inverted stop signal STOPB obtained by inverting the stop signal STOP in the inverter G
4
is input to the gate of the PMOS transistor M
13
.
The operation of the reference voltage generator circuit RG is described below. The stop signal STOP is a

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