Semiconductor integrated circuit device subjected to scan-testin

Details Semiconductor integrated circuit device subjected to scan-testin Semiconductor integrated circuit device subjected to scan-testin

1988-03-30

1990-01-30

Atkinson, Charles E.

Excavating

G01R 3128

Patent

active

048978388

ABSTRACT:
A semiconductor integrated circuit device suitable for an internal logic diagnostic test includes an input terminal pin for receiving data including test data, and an output terminal pin for generating data including operation result data of the device. An internal logic circuit of the device is divided into internal logic units. Scanning flip-flop circuits are arranged between these internal logic units. The scanning flip-flop circuits includes a first plurality of flip-flop circuits arranged along a first scanning direction between the input and output terminals, and a second plurality of flip-flop circuits branched off from each of the first flip-flop circuits and arranged along a second scanning direction. The first flip-flop circuits are preferably constituted by 2-input/2-output flip-flop circuits series-connected along the first scanning direction. Each 2-input/2-output flip-flop circuit has a first pair of scanning input and scanning output, and a second pair of scanning input and scanning output, which are selectively designated.

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"Designing Digital Circuits with Easy Testable Consideration," Test Conf. pp. 98-102, S. Fumatsu, N. Wakatsuki, and A. Yamada, 1978.
"A Logic Design Structure for LSI Testability", Proc. 14th DA Conf. p. 462, E. B. Eichelberger and T. W. Williams, 1977.

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