Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-03-22
2002-06-25
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S201000, C365S189050, C365S230060
Reexamination Certificate
active
06411563
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a semiconductor integrated circuit device including a memory core and a logic circuit mounted on a single chip.
2. Description of the Background Art
In a recent technology of a semiconductor integrated circuit, circuit structures aimed at further technological innovation are being practically available for improving packing densities and operation speeds. More specifically, for reducing manufacturing costs of semiconductor integrated circuit devices and increasing operation speeds thereof, technical developments have been made to provide a semiconductor integrated circuit device, in which a semiconductor memory device and a semiconductor logic circuit device are mounted on a single chip in a mixed fashion.
FIG. 24
is a schematic block diagram of a conventional semiconductor integrated circuit device, which is provided with a semiconductor memory device and a semiconductor logic circuit device in a mixed fashion, and particularly shows a structure of a semiconductor integrated circuit device
8000
disclosed in Japanese Patent Laying-Open No.
10-283777.
Referring to
FIG. 24
, semiconductor integrated circuit device
8000
in the prior art includes a semiconductor memory device such as a synchronous dynamic random access memory core (which will be referred to as an “SDRAM core” hereinafter)
104
, a logic circuit
102
and an SDRAM controller
103
which is a fast interface arranged between logic circuit
102
and SDRAM core
104
for fast operation of circuitry provided with logic circuit
102
and SDRAM core
104
in a mixed fashion.
More specifically, semiconductor integrated circuit device
8000
is provided with an external terminal group
101
which is employed for receiving external control signals, and includes a terminal group
110
for applying control signals and data to logic circuit
102
, and an external clock input terminal
105
for externally applying a clock signal to a clock producing circuit
106
.
SDRAM controller
103
operates in accordance with a clock signal CLK applied from clock producing circuit
106
, and is controlled by logic circuit
102
to apply to SDRAM core
104
internal control signals such as an activating signal ACT(
114
), a precharge signal PRC(
115
), a write signal WRITE(
116
), a read signal READ(
117
) and a refresh signal REF(
118
).
An input synchronization latch circuit, i.e., a latch circuit
8122
for input latch latches a signal supplied to SDRAM core
104
, and a timing producing circuit
8123
produces an internal operation signal to be applied to a memory array
8121
in accordance with the output of input synchronization latch circuit
8122
. Input synchronization latch circuit
8122
operates in synchronization with clock signal CLK sent from clock producing circuit
106
.
An output control circuit
8124
sends the output of memory array
8121
to SDRAM controller
103
in synchronization with internal dock signal CLK.
Thus, the signals supplied to external terminal group
101
are successively converted when they pass through logic circuit
102
, SDRAM controller
103
, input synchronization latch circuit
8122
and timing producing circuit
8123
, and then are applied to memory array
8121
.
The internal operation signals applied to memory array
8121
include a signal for designating the time of activation of a word line, a signal for instructing start and stop of precharging of a bit line pair, a signal for instructing start and stop of an operation of a sense amplifier, a memory cell column select signal for selectively performing reading of data from the bit line pair, a read amplifier activating signal for activating a read amplifier which reads out data from the bit line pair, and a write driver activating signal for driving a write drive transmitting write data onto the bit line pair.
The internal control signals applied from SDRAM controller
103
to SDRAM core
104
are already converted into the internal control signals for operating timing producing circuit
8123
.
In the case where the SDRAM is an SDRAM memory of one chip, this SDRAM memory receives the external control signals from the external terminals, and operates in accordance with the received external control signals. However, a general-purpose single SDRAM can use only a restricted number of external terminals, and therefore is generally and internally provided with a decoder for decoding such external control signals.
If such a command decoder for decoding commands, which are provided by externally supplied control signals, is employed in SDRAM core
104
shown in
FIG. 24
, a delay time of this command decoder delays the operation of SDRAM core
104
.
The structure shown in
FIG. 24
is not provided with such a command decoder, and thereby can operate faster.
FIG. 25
is a timing chart for showing an operation of semiconductor integrated circuit device
8000
shown in FIG.
24
.
For example, internal control signal ACT(
114
) is produced within SDRAM controller
103
in synchronization with rising edge timing of internal clock signal CLK at a time t
0
. Therefore, it is issued from SDRAM controller
103
with a delay of a time t(control) from the rising edge of internal clock signal CLK at time t
0
.
Assuming that input synchronization latch circuit
8122
has a setup time t(setup), the following formula must be satisfied so that input synchronization latch circuit
8122
can take in signal ACT(
114
) at a time t
1
after one cycle t(CLK) from time t
0
of rising edge of signal ACT(
107
).
t
(
CLK
)>
t
(control)+
t
(setup)
Similar relationship must be satisfied in connection with other internal control signals such as signals PRC(
115
), WRITE(
116
) and READ(
117
).
Since the minimum cyclic period of internal clock signal CLK does not require a time for decoding in SDRAM core
104
as described above, this can improve the operation speed.
The structure of semiconductor integrated circuit device
8000
described above can improve the operation speed, but suffers from the following problem.
In a process of designing semiconductor integrated circuit device
8000
, it is generally desired that a portion forming SDRAM core
104
employs the same circuit structure as that for the device including logic circuit
102
of a different structure.
On the other hand, it is desired that logic circuit
102
employs the same circuit structure as that, which has already been designed and proven.
If the design of logic circuit
102
is based on the presumption that it issues control signals for a general purpose SDRAM chip, SDRAM core
104
is configured to receive internal control signals, which are prepared by decoding general-purpose SDRAM control signals, from an interface. Accordingly, SDRAM controller
103
must have a function of converting the SDRAM control signal sent from logic circuit
102
to the internal control signals.
The design data which has been conventionally accumulated for logic circuit
102
includes not only data for a system, where external control signals for a specific general-purpose SDRAM are sent to the interface, but also data for an external command system, in which external control signals, e.g., for a clock synchronous EDO-DRAM (Extended Data Out-DRAM) are sent to an interface.
Accordingly, the interface for the logic circuit, of which design data has been accumulated, must be redesigned whenever the interface specifications of the memory for data transmission are changed, and in other words, whenever the external command system is changed. This means that SDRAM controller
103
must be redesigned in accordance with the interface specifications of logic circuit
102
and corresponding SDRAM core
104
every time the above change occurs, and therefore lowers design efficiencies.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor integrated circuit device, in which a logic circuit and a memory circuit are arranged in a mixed fashion, and are efficiently interfaced with each other while util
Kawasaki Toshiaki
Tsuji Takaharu
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