Semiconductor integrated circuit device of master slice approach

Details Semiconductor integrated circuit device of master slice approach Semiconductor integrated circuit device of master slice approach

1990-02-07

1992-03-31

Hille, Rolf

357 43, 357 59, 357 35, 357 51, H01L 2704

Patent

active

051012588

ABSTRACT:
In a semiconductor integrated circuit device of master slice approach according to this invention, regions on basic elements which are not used and isolation areas serve as wiring regions. Resistive elements are formed on the regions on the basic elements which are not used and the isolation areas. A high integration level can be obtained, circuit layout can be facilitated, and versatility of circuit design can be improved.

REFERENCES:
patent: 4579600 (1986-04-01), Shah et al.
patent: 4682202 (1987-07-01), Tanizawa
patent: 4748488 (1988-05-01), Suzuki et al.
patent: 4949153 (1990-08-01), Hirao et al.
IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr., 1985, "Diagonal Layout of Gate Array", pp. 6727-6728.
8107 I.E.E.E. Journal of Solid State Circuits, SC-21 (1986) Oct., No. 5, "A Bipolar 18K-Gate Variable Size Cell Masterslice" by Takashi Nishimura et al., pp. 727-732.
8032 Electronics 59 (1986) Sep., No. 30, "Fairchild's Radical Process For Building Bipolar VLSI", pp. 55-59.
8032 Electronics, 61 (1988) Feb. 4, No. 3, "LSI Logic Arrays Boost Both Drive and Density", by Samuel Weber, pp. 63-64.

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