Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2006-12-28
2010-12-21
Behm, Harry (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S267000, C323S281000
Reexamination Certificate
active
07855536
ABSTRACT:
Source voltage and substrate voltage are supplied to a semiconductor integrated circuit1E from the regulator circuits11C and21C of a power supply circuit1C via a power detection compensating circuit1D. The power efficiency value of a regulator is stored in the resistor file13D, various detection information and power values are input to an operator14D, the power values and the power efficiency values of the regulator circuits11C and21C are accumulated, and the power sum of a semiconductor integrated circuit1E and a power supply circuit1C are output. Minimum power implementation information corresponding to the various detection information of the semiconductor integrated circuit1E is stored in an LUT15D. Variable resistances R1aand R2aare controlled for determining the reference voltage values of the regulator circuits11C and21C so that the power sum is the minimum power value by comparing the minimum power implementation information with the output14D.
REFERENCES:
patent: 6141762 (2000-10-01), Nicol et al.
patent: 6646424 (2003-11-01), Zinn et al.
patent: 6771052 (2004-08-01), Ostojic
patent: 6903945 (2005-06-01), Kitano
patent: 6967522 (2005-11-01), Chandrakasan et al.
patent: 7353410 (2008-04-01), Desai et al.
patent: 7581122 (2009-08-01), Kim et al.
patent: 2002/0158618 (2002-10-01), Hiraki et al.
patent: 2003/0065960 (2003-04-01), Rusu et al.
patent: 2003/0234636 (2003-12-01), Ruan et al.
patent: 2004/0193929 (2004-09-01), Kuranuki
patent: 2005/0162146 (2005-07-01), Kobayashi
patent: 2005/0219883 (2005-10-01), Maple et al.
patent: 2005-197411 (2005-07-01), None
Keshavarzi, et al., “Effectiveness of Reverse Body Bias for Leakage Control in Scaled Dual Vt CMOS ICs”, ISLPED '01, Aug. 6-7, 2001, pp. 207-212, ACM.
Behm Harry
McDermott Will & Emery LLP
Panasonic Corporation
LandOfFree
Semiconductor integrated circuit device minimizing the total... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device minimizing the total..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device minimizing the total... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4225683