Semiconductor integrated circuit device including means for redu

Details Semiconductor integrated circuit device including means for redu Semiconductor integrated circuit device including means for redu

1981-10-26

1984-10-16

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200B, 307443, 307543, 357 236, H03K 3013

Patent

active

044777361

ABSTRACT:
In an MOS memory, a reference voltage is generated to determine an input threshold voltage of the input circuit. Noise fed from various signal wirings to the reference voltage wiring via stray capacitances is reduced by a decoupling capacitance formed between the reference voltage wiring and the ground wiring. The decoupling capacitance, however, permits relatively large levels of noise induced on the ground wiring by changes in the operation current of the circuit to be transmitted to the reference voltage wiring. According to this invention, a capacitance which forms a pair with the decoupling capacitance is provided between the power-supply wiring and the reference voltage wiring. Noise induced on the power-supply wiring by a change in the operation current of the circuit is substantially opposite in polarity to the noise induced on the ground wiring. Therefore, the noise fed from the ground wiring to the reference voltage wiring is cancelled by the capacitance provided between the power-supply wiring and the reference voltage wiring.

REFERENCES:
patent: 3200260 (1965-08-01), Fisk et al.
patent: 3959665 (1976-05-01), Gilbreath et al.
patent: 4095163 (1978-06-01), Montague

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