Semiconductor integrated circuit device including a plurality of

Details Semiconductor integrated circuit device including a plurality of Semiconductor integrated circuit device including a plurality of

1991-09-30

1994-10-18

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Plural blocks or banks

365 51, 365 63, G11C 800

Patent

active

053574788

ABSTRACT:
A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.

REFERENCES:
patent: 4660174 (1987-04-01), Takemae et al.
patent: 4837747 (1989-06-01), Dosaka et al.
patent: 5040152 (1991-08-01), Voss et al.
patent: 5208782 (1993-05-01), Sakuta et al.
patent: 5210723 (1993-05-01), Bates et al.
patent: 5222047 (1993-06-01), Matsuda et al.
1987 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 1987, "A 70ns 4Mb DRAM in a 300mil DIP using 4-Layer Poly", Mochizuki et al.
Abstract of "Nikkei Macro Device", special edition, No. 1, May 1987, pp. 117-130, 63.7MM.sup.2 4M DRAM with Proportionally Reduced Stacked Cells.

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