Semiconductor integrated circuit device including a plurality of

Details Semiconductor integrated circuit device including a plurality of Semiconductor integrated circuit device including a plurality of

1999-02-02

2000-03-14

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular connection

36518511, 36518517, G11C 700

Patent

active

060381701

ABSTRACT:
A nonvolatile memory of a hierarchical bit line structure having hierarchical bit lines includes a plurality of sub-bit lines. Each sub-bit line is connected to an appropriate main bit line through a first and a second selection MISFET. The first selection MISFET has a thin gate insulating film and is used for read operations only. The second MISFET has a thick gate insulating film and is used at least for write operations. In a write operation, the first selection MISFET has its drain or its gate supplied with a predetermined bias voltage so that the gate insulating film of the transistor will not be subjected to a voltage defeating the dielectric strength of the film.

REFERENCES:
patent: 5057448 (1991-10-01), Kuroda
patent: 5392238 (1995-02-01), Kirisawa
patent: 5440509 (1995-08-01), Momodomi et al.
1995 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 122-123.
1994 IEEE Journal of Solid-State Circuits, vol. 29, No. 4, Apr. 1994, pp. 454-460.
1987 IEDM Technical Digest, pp. 560-563.

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