Semiconductor integrated circuit device having wiring for clock

Details Semiconductor integrated circuit device having wiring for clock Semiconductor integrated circuit device having wiring for clock

1992-11-12

1994-10-11

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

257208, 257776, 257773, 257786, 307406, 3074821, H01L 4900, H01L 2348, H01L 2944, H01L 2952

Patent

active

053550048

ABSTRACT:
A semiconductor integrated circuit device wherein terminals other than clock signal terminals in circuit blocks are connected via a first wiring layer to a clock signal source and only the clock signal terminals in the blocks are connected via a second wiring layer to the source. The second wiring layer is formed above the first wiring layer and is connected to the clock signal terminals. Since the second wiring layer is dedicated to the clock signal, clock signal wiring can be laid out as desired when a layout is designed by a hierarchical design technique. There is no chance that propagation characteristics of the clock signals to the blocks deviates, and a cell area can be reduced. Preferably, a third wiring layer connected to the second wiring layer is furthermore provided for dedication to the clock signal.

REFERENCES:
patent: 4197555 (1980-04-01), Uehara et al.
patent: 4924290 (1990-05-01), Enkaku et al.
patent: 4990992 (1991-02-01), Uchida
patent: 5049969 (1991-09-01), Orbach et al.
patent: 5055716 (1991-10-01), El Gamel

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