Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Patent
1993-11-12
1995-10-31
Hille, Rolf
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
257626, 257735, 257786, H01L 23544
Patent
active
054632455
ABSTRACT:
A semiconductor integrated circuit device of this invention includes a semiconductor substrate having an active region arranged in a main surface area and an inactive region arranged in a peripheral portion of the main surface area. A semiconductor integrated circuit is formed in the active region in the main surface area of the semiconductor substrate. A connection electrode is formed on the inactive region. One end of a lead is connected to the connection electrode and the other end thereof is arranged to extend to the exterior of the semiconductor substrate. The semiconductor integrated circuit and the connection electrode are electrically connected to each other via an impurity diffusion region. At least the active region of the semiconductor substrate, the connection electrode, part of the lead arranged on the main surface of the semiconductor substrate, and the impurity diffusion region are covered with a sealing body having a sealing substrate.
REFERENCES:
patent: 4862322 (1989-08-01), Bickford et al.
patent: 5136354 (1992-08-01), Morita et al.
patent: 5233130 (1993-08-01), Nishino
patent: 5296745 (1994-03-01), Shirai et al.
patent: 5317194 (1994-05-01), Sako
"Large-Capacity Memory Mode By Chip Lamination Mounting", Hatada et al., Third Microelectronics Symposium, 86-88 (Jul. 1989).
"A Large Memory Board by Chip Lamination Mounting," of Third Micro-electronics Symposium (MES '89), Jul. 1989, pp. 86-88.
Hille Rolf
Kabushiki Kaisha Toshiba
Potter Roy
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