Semiconductor integrated circuit device having pseudo-tuning...

Details Semiconductor integrated circuit device having pseudo-tuning... Semiconductor integrated circuit device having pseudo-tuning...

1998-12-16

2002-09-03

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Circuit interruption by thermal sensing

C361S115000

Reexamination Certificate

active

06445558

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more specifically to a semiconductor integrated circuit device having a configuration for pseudo-tuning an internal power-supply voltage.
2. Description of the Background Art
Because of the influence of process variation and the like, an internal power-supply voltage of a device after the completion of a wafer process does not take a desired value. Thus, there is a need to tune the internal power-supply voltage before the actual use.
A power-supply tuning circuit
900
provided in a conventional semiconductor integrated circuit device will be described with reference to FIG.
10
. As an example, a configuration in which an internal power-supply voltage is generated using two pads PAD
1
and PAD
2
is shown in FIG.
10
.
The conventional power-supply tuning circuit
900
shown in
FIG. 10
is provided with power-supply circuits
901
and
902
, switching circuits
911
and
912
, and NAND circuits
921
and
922
.
NAND circuit
921
receives at its inputs a tuning signal applied from pad PAD
1
and a pseudo-tuning on signal TUNE. NAND circuit
922
receives at its inputs a tuning signal applied from pad PAD
2
and pseudotuning on signal TUNE. Pseudo-tuning on signal TUNE is applied from an external pad PAD
0
.
Switching circuits
911
and
912
each include power-supply selection transistors N
90
and N
91
. Power-supply selection transistors N
90
and N
91
in switching circuit
911
switch on/off in response to a control signal S
1
. Power-supply selection transistors N
90
and N
91
in switching circuit
912
switch on/off in response to a control signal S
2
.
Switching circuit
911
supplies the outputs from NAND circuits
921
and
922
to a corresponding power-supply circuit
901
in response to control signal S
1
. Switching circuit
912
supplies the outputs from NAND circuits
921
and
922
to a corresponding power-supply circuit
902
in response to control signal S
2
.
When the logic high or “H” level pseudo-tuning on signal TUNE is applied from external pad PAD
0
, power-supply tuning circuit
900
enters a pseudo-tuning mode. In the pseudo-tuning mode, NAND circuits
921
and
922
each output a signal corresponding to a tuning signal applied from outside. Switching circuits
911
and
912
each select a power-supply circuit which perform pseudo-tuning.
Power-supply circuit
901
outputs a voltage in response to the combination of signals (tuning data) received from pads PAD
1
and PAD
2
. The output from power-supply circuit
901
is referred to as an internal power-supply voltage Vref
1
.
Power-supply circuit
902
outputs a voltage in response to the combination of signals (tuning data) received from pads PAD
1
and PAD
2
. The output from power-supply circuit
902
is referred to as an internal power-supply voltage Vref
2
.
The configuration of a power-supply circuit included in the conventional power-supply tuning circuit shown in
FIG. 10
will be described with reference to
FIG. 11. A
power-supply circuit
950
shown in
FIG. 11
corresponds either of the power-supply circuits
901
and
902
shown in FIG.
10
.
Power-supply circuit
950
shown in
FIG. 11
includes NMOS transistors
26
and
27
, PMOS transistors
21
,
22
, and
23
, and fuses
24
and
25
.
Each of the PMOS transistors
21
,
22
, and
23
is a transistor having a specific resistance value. PMOS transistors
21
,
22
, and
23
are connected in series between an external power-supply voltage extVCC and a ground potential GND, and the gate electrode of each transistor is connected to ground potential GND.
NMOS transistor
26
and fuse
24
are connected in series between one conductive terminal and the other conductive terminal of PMOS transistor
21
. NMOS transistor
27
and fuse
25
are connected in series between one conductive terminal and the other conductive terminal of PMOS transistor
22
.
A pseudo-tuning data input node
2
a
receives an output from NAND circuit
921
shown in
FIG. 10. A
pseudo-tuning data input node
2
b
receives an output from NAND circuit
922
shown in FIG.
10
.
The gate electrode of NMOS transistor
26
is connected to pseudo-tuning data input node
2
a
. The gate electrode of NMOS transistor
27
is connected to pseudo-tuning data input node
2
b.
An internal power-supply voltage Vref (corresponding to Vref
1
or Vref
2
in
FIG. 10
) is output from a node
2
c
connecting PMOS transistors
22
and
23
. The value of internal power-supply voltage Vref is determined by the ratio of the resistance value between node
2
c
and ground potential GND with respect to the resistance value between node
2
c
and external power-supply voltage extVCC.
In the configuration shown in
FIG. 11
, the resistance value between node
2
c
and the external power-supply voltage can be selected from four levels by switching on/off each of the NMOS transistors
26
and
27
(or fuses
24
and
25
).
In the pseudo-tuning mode (where pseudo-tuning on signal TUNE is activated), each of the NMOS transistors
26
and
27
is switched on/off based on a tuning signal while a fuse is constantly kept ON (fuse is in the connected state). Thus, the states in which the fuse is ON/OFF (connected/disconnected) are emulated. From observed result using a tester, an optimal tuning data (referred to as a tuning code) is determined.
When the internal power-supply voltage is specified for a finished product, NMOS transistors
26
and
27
are kept ON constantly, and fuse
24
or
25
is selectively blown (ON/OFF) by a laser trimmer based on the determined tuning code.
In a conventional power-supply tuning circuit, the same plurality of pads are used to perform pseudo-tuning for a plurality of power-supply circuits, as shown in FIG.
10
and FIG.
11
. It is therefore impossible to perform pseudo-tuning simultaneously for a plurality of power-supply circuits.
Consequently, in the conventional pseudo-tuning mode in a wafer test, pseudo-tuning is required for each power-supply circuit in order to determine the optimal tuning code corresponding to each circuit.
In addition, conventionally, it is impossible to set the optimal tuning code for each of the power-supply circuits at the same time. Therefore, in the wafer test, the internal power-supply voltage used is adjusted by applying it from outside.
Moreover, in a conventional power-supply tuning circuit, since the power-supply circuit does not have the current drivability, it is necessary, for example, to tune, to a higher potential, the potential (logic low or “L” level) inappropriate to be monitored from outside.
SUMMARY OF THE INVENTION
Thus, the present invention provides a semiconductor integrated circuit device which is capable of performing simultaneous pseudo-tuning for a plurality of power-supply circuits.
Moreover, the present invention provides a semiconductor integrated circuit device which can pseudo-tune without the use of a plurality of pads.
Furthermore, the present invention provides a semiconductor integrated circuit device which is capable of performing accurate pseudo-tuning with ease.
The semiconductor integrated circuit device according to an aspect is provided with a plurality of power-supply generation circuits, each including a fuse for generating a desired internal voltage when being blown, a latch circuit for latching tuning data for performing pseudo-tuning, and an emulation circuit for emulating, in response to the data latched by the latch circuit, a blow state of the fuse to emulate outputting of the internal voltage, and a plurality of supply control circuits being disposed corresponding to the plurality of power-supply generation circuits respectively and each controlling supplying of the tuning data to the corresponding power-supply generation circuit.
Thus, one advantage of the present invention is that simultaneous pseudo-tuning for a plurality of power-supply circuits becomes possible with a latch circuit for latching the data for pseudo-tuning provided for each of the plura

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