Semiconductor integrated circuit device having pads at periphery

Details Semiconductor integrated circuit device having pads at periphery Semiconductor integrated circuit device having pads at periphery

1992-01-23

1993-06-01

LaRoche, Eugene R.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

257508, 257503, 257700, 257691, H01L 2348

Patent

active

052162800

ABSTRACT:
For increasing the number of pads to be connected to external terminals such as leads of a lead frame without increasing an area of a semiconductor IC chip, pads are disposed at a periphery of the chip in such a manner that they are arranged in at least first and second rows, to which at least first and second groups of interconnection layers insulated through an interval insulator are electrically connected, respectively.

REFERENCES:
patent: 4631569 (1986-12-01), Calhoun
patent: 4646126 (1987-02-01), Iizuka
patent: 4688070 (1987-08-01), Shiotari et al.
patent: 4734754 (1988-03-01), Nikawa
patent: 4746965 (1988-05-01), Nishi
patent: 4841354 (1989-06-01), Inabe
patent: 4881029 (1989-11-01), Kawamura
patent: 4905068 (1990-02-01), Satoh et al.
patent: 4916521 (1990-04-01), Yoshikawa et al.
patent: 5016087 (1991-05-01), Haug et al.
patent: 5148263 (1992-09-01), Hamai
Kenyon et al., "Two-level wiring system", IBM TDB, vol. 19, No. 5, Oct. 1976, pp. 1628-1629.

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit device having pads at periphery does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit device having pads at periphery, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device having pads at periphery will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1816972