Semiconductor integrated circuit device having output buffer

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver

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Details

327112, 327111, 327109, H03B 100, H03K 300

Patent

active

061631779

ABSTRACT:
An output buffer includes an NAND circuit, a first N channel MOS transistor connected between a power supply node and an output node, a second N channel MOS transistor connected between the output node and a ground node, the first to third drive circuits, and a delay circuit. The power supply voltage is first supplied to the gate of the second N channel MOS transistor by the second drive circuit. After a delay time delayed by the delay circuit has passed, boosted voltage is supplied to the gate of the second N channel MOS transistor by the third drive circuit. Accordingly, the output buffer is not influenced by the ringing and the pull-down characteristic improves.

REFERENCES:
patent: 5334889 (1994-08-01), Hisaka
patent: 5338988 (1994-08-01), Yamamura et al.
patent: 5396463 (1995-03-01), Kim et al.
patent: 5912569 (1999-06-01), Alleven
patent: 5952875 (1999-09-01), Yosefin et al.
patent: 6037811 (2000-03-01), Ozguc

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