Semiconductor integrated circuit device having means for peak cu

Details Semiconductor integrated circuit device having means for peak cu Semiconductor integrated circuit device having means for peak cu

1996-12-17

1998-08-11

Mai, Son

Static information storage and retrieval

Addressing

Plural blocks or banks

365194, 365222, G11C 800

Patent

active

057936943

ABSTRACT:
The present invention is a method and apparatus for reducing the peak current for all the bit mats during a CAS-before-RAs refresh operation of a DRAM. To this end, a circuit is created to detect a CAS-before-RAS refresh operation. When a CBR refresh is detected, the amplifying of the bit mats are offset from each other, thereby staggering the time when each bit mat draws its peak current. In an alternative embodiment, when a CBR refresh is detected, the activation of the word lines are offset from each other, thereby staggering the time when each bit mat draws its peak current.

REFERENCES:
patent: 4627033 (1986-12-01), Hyslop
patent: 4912678 (1990-03-01), Mashiko
patent: 5208782 (1993-05-01), Sakuta et al.
patent: 5367493 (1994-11-01), Yamagata
patent: 5371715 (1994-12-01), Kim
patent: 5442588 (1995-08-01), Runas

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit device having means for peak cu does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit device having means for peak cu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device having means for peak cu will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-396468